VMINU.VX

RISC-V VMINU.VX Instruction Details

Q: How does VMINU.VX differ from the signed form?

VMINU.VX uses unsigned integer ordering; the non-U form uses signed integer ordering. Both write back the selected source's SEW-bit pattern; the .vx scalar source first follows the XLEN/SEW scalar rule.

Q: Does VMINU.VX produce overflow or exception flags?

No. VMINU.VX compares and selects a source element pattern; it does not perform add/subtract overflow computation and does not set integer or floating-point exception flags.

Q: How do vm and v0.t affect VMINU.VX?

With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.

Instruction ManualR-type

Select the smaller value element by unsigned integer ordering and write the selected SEW-bit pattern to vd.

Instruction Syntax

vminu.vx vd, vs2, rs1, vm

Operand Breakdown

vd: mask destination register, with one Boolean result bit per element.

vs2/vs1 or scalar source: compared at the current SEW.

vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.

VVector IntegerMin/Max

Related Search Terms

VMINU.VX instruction RISC-V VMINU.VX vminu.vx syntax vminu.vx encoding RVV unsigned minimum vminu.vx mask unsigned vector compare

Instruction Behavior

VMINU.VX is the RISC-V V extension vector-scalar unsigned minimum instruction. Each active body element reads vs2[i] and integer scalar x[rs1], compares them by unsigned integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.

VMINU.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMINU compares active elements as unsigned integers and writes the smaller SEW-bit pattern to vd.

Instruction input

vminu.vx

vdUse v0-v31vs2Use v0-v31rs1Use x0-x31 or ABI namevmexecution mask control

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

OP-V encodingvminu.vx

funct6

000100

vs2

01000

rs1

01011

funct3

100

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

min

x11

0x0013

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vminu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned minimum, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMINU.VX compares vs2 with x[rs1] after the XLEN/SEW scalar rule lane by lane for active elements within the current vl and selects the smaller value by unsigned integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference or produce overflow or exception flags.

VMINU uses OP-V vector-arithmetic encoding with funct6=000100; the .vx form is selected by funct3=100.

The core semantic relation compares vs2[i] with the x[rs1] scalar after the XLEN/SEW truncation or sign-extension rule for active elements by unsigned integer ordering, then writes the smaller value's original SEW-bit pattern to vd[i].

VMINU/VMAXU use unsigned integer ordering; comparison and selection use the SEW-width unsigned values.

Only body elements within the current vl are processed; vm=0 uses the v0 mask and vm=1 is unmasked, while mask-off and tail destination elements follow the current vtype policies.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations, Vector Integer Min/Max Instructions

Vector Execution Context

When reading VMINU.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Data Clipping

Understand this scenario with real code like «vminu.vx v4, v8, a1, v0.t».

Thresholding

Understand this scenario with real code like «vminu.vx v4, v8, a1, v0.t».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

VMINU selects one source element pattern; it is not addition, subtraction, or a saturating operation.

Unsigned forms compare the SEW bit patterns as unsigned integers, so a value with the top bit set is usually larger than one with the top bit clear.

The VX form takes its second source from integer register x[rs1]; if XLEN>SEW the low SEW bits are used, and if XLEN<SEW the value is sign-extended to SEW before comparison.

With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.

FAQ

How does VMINU.VX differ from the signed form?