How does VMAXU.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.
VMAXU.VV
RISC-V VMAXU.VV Instruction Details
Instruction ManualR-typeCompute the element-wise unsigned maximum and write vd.
Instruction Syntax
vmaxu.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerMin/Max
Instruction Behavior
VMAXU.VV is a RISC-V V element-wise unsigned maximum instruction. For each active element within vl, it compares vs2 with vs1 using unsigned integer ordering and writes the larger value to vd.
Quick Understanding & Search Notes
VMAXU.VV writes only active elements; integer overflow keeps the low SEW bits and does not trap.
Vector-scalar .vx forms use x[rs1], while vector-vector .vv forms use vs1.
Results are written at SEW width; high-half multiply explicitly returns the high SEW bits of the 2*SEW product.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
Data Clipping
Understand this scenario with real code like «vmaxu.vv v8, v4, v6».
Thresholding
Understand this scenario with real code like «vmaxu.vv v8, v4, v6».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Differs from vmin in signed semantics