How does VMAXU.VV differ from the signed form?
VMAXU.VV uses unsigned integer ordering; the non-U form uses signed integer ordering. Both write back the selected source element's SEW-bit pattern.
VMAXU.VV
RISC-V VMAXU.VV Instruction Details
Instruction ManualOPIVVSelect the larger value element by unsigned integer ordering and write the selected SEW-bit pattern to vd.
Instruction Syntax
vmaxu.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.
vs1 supplies the same-lane SEW-bit second source; equal vector sources and old vd must describe the same initial register contents.
Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.
VVector IntegerMin/Max
Extension condition: Requires V 1.0, enabled vector state, valid vtype, and supported element widths.
Instruction Behavior
VMAXU.VV is the RISC-V V extension vector-vector unsigned maximum instruction. Each active body element reads vs2[i] and vs1[i], compares them by unsigned integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
VMAXU.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMAXU compares active elements as unsigned integers and writes the larger SEW-bit pattern to vd.
Instruction input
vmaxu.vv
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmaxu.vv
funct6
000110
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
max
max
max
max
max
max
max
max
v12
0x000d
0x0016
0x001f
0x0028
0x0031
0x003a
0x0043
0x004c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmaxu.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned maximum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMAXU.VV compares vs2 with vs1 lane by lane for active elements within the current vl and selects the larger value by unsigned integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference.
32-bit OP-V encoding: opcode=1010111, funct6=000110, funct3=000 (OPIVV). Syntax places vs2 before vs1/rs1.
Active elements compare vs2 and the second source using unsigned integer ordering and write the larger value’s SEW-bit pattern to vd.
vs1 supplies the same-lane SEW-bit second source; equal vector sources have one set of initial values.
Body elements satisfy vstart≤i<vl. Omitting v0.t means vm=1; including it means vm=0, enabling only masked-on body elements. Prestart is unchanged; inactive/tail elements follow vma/vta, with agnostic elements retaining old values or becoming all ones.
VL=0 or vstart≥vl updates no destination elements, including tails. Normal completion resets vstart=0 and leaves vl unchanged. Masked vd cannot cover v0, and v0 cannot be read as both an EEW=1 mask and SEW data.
Vector Execution Context
vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.
vs1 supplies the same-lane SEW-bit second source; equal vector sources and old vd must describe the same initial register contents.
Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.
Common Usage Scenarios
Elementwise maximum selection
Assume RV32/RV64 V, enabled vector state, supported e32,m1, and VLEN≥128; after vsetivli, vl=4, vstart=0, ta/ma, with initialized sources and v0.mask=[1,0,1,1]. v8=[0xffffffff,2,0x80000000,7], v12=[3,3,3,3] → v4=[0xffffffff,policy,0x80000000,7]. policy means mask-agnostic: retain the old value or write all ones; tails are likewise not guaranteed zero.
Pre-Use Checklist
Syntax Check
- vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.
- vs1 supplies the same-lane SEW-bit second source; equal vector sources and old vd must describe the same initial register contents.
Semantic Check
- Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
- Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.
Pitfalls / Common Confusions
VMAXU selects one source element pattern; it is not addition, subtraction, or a saturating operation.
In unsigned comparison, a SEW-bit value with the top bit set is larger than one with the top bit clear.
The VV form takes its second source from vector register vs1 and does not read an integer scalar register.
With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.
FAQ
How does VMAXU.VV handle masking and tails?
vm=0 uses v0.t and enables only elements where vstart≤i<vl and the mask bit is 1. vm=1 is unmasked. Prestart is unchanged; inactive/tail elements follow vma/vta. With VL=0 or vstart≥vl, even tails are unchanged.