VMAXU.VX

RISC-V VMAXU.VX Instruction Details

Q: How does VMAXU.VX differ from the signed form?

VMAXU compares unsigned values; VMAX compares signed values. Both select the original SEW bits. The .vx scalar follows XLEN/SEW rules.

Q: How is the VMAXU.VX scalar adapted to SEW?

Use the low SEW bits if XLEN>SEW; sign-extend if XLEN<SEW, even for this unsigned comparison. x0 supplies zero.

Q: How do vm and v0.t affect VMAXU.VX?

vm=0 executes body lanes with v0.t=1; vm=1 executes all body lanes. Inactive and tail results follow vtype policies.

Instruction ManualOPIVX

Select the larger value element by unsigned integer ordering and write the selected SEW-bit pattern to vd.

Instruction Syntax

vmaxu.vx vd, vs2, rs1, vm

Operand Breakdown

vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.

rs1 selects an integer x-register: take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.

Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.

Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.

VVector IntegerMin/Max

Related Search Terms

VMAXU.VX instruction RISC-V VMAXU.VX vmaxu.vx syntax vmaxu.vx encoding vmaxu.vx unsigned maximum vmaxu.vx mask vmaxu.vx unsigned vector compare

Instruction Behavior

VMAXU.VX is the RISC-V V extension vector-scalar unsigned maximum instruction. Each active body element reads vs2[i] and integer scalar x[rs1], compares them by unsigned integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.

VMAXU.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMAXU compares active elements as unsigned integers and writes the larger SEW-bit pattern to vd.

Instruction input

vmaxu.vx

vdUse v1-v31; v0 is the execution maskvs2Use v1-v31; v0 supplies the EEW=1 mask/carryrs1Use x0-x31 or ABI namevmexecution mask control

Require valid vtype, enabled VS, and supported SEW. Only body elements are shown; VL=0 updates no destination elements, including tails. Same-EEW sources/destination may overlap. When v0 supplies EEW=1 mask/selection bits, it cannot also supply SEW data or be vd.

Execution Context

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvmaxu.vx

funct6

000110

vs2

01000

rs1

01011

funct3

100

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

max

x11

0x0013

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vmaxu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned maximum, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

For active elements, VMAXU.VX selects the larger unsigned value of vs2[i] and the XLEN/SEW-adapted x[rs1], writing its SEW-bit pattern to vd[i].

OP-V: funct6=000110, funct3=100 (OPIVX).

Body elements execute; vm=0 uses v0 and vm=1 is unmasked. Mask-off and tail results follow vtype policies.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — V 1.0, Vector Integer Min/Max Instructions

Vector Execution Context

vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.

rs1 selects an integer x-register: take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.

Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Data Clipping

Assume RV32/RV64 V, enabled vector state, supported e32,m1, and VLEN≥128; after vsetivli, vl=4, vstart=0, ta/ma, with initialized sources and v0.mask=[1,0,1,1]. v8=[0xffffffff,2,0x80000000,7], x11=3 → v4=[0xffffffff,policy,0x80000000,7]. policy means mask-agnostic: retain the old value or write all ones; tails are likewise not guaranteed zero.

Thresholding

Pre-Use Checklist

Syntax Check

vd is the SEW-bit destination; compare vs2 and the second source by unsigned ordering and select the larger source pattern.
rs1 selects an integer x-register: take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.

Semantic Check

Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.

Pitfalls / Common Confusions

VMAXU selects one source element pattern; it is not addition, subtraction, or a saturating operation.

Unsigned forms compare the SEW bit patterns as unsigned integers, so a value with the top bit set is usually larger than one with the top bit clear.

The VX form takes its second source from integer register x[rs1]; if XLEN>SEW the low SEW bits are used, and if XLEN<SEW the value is sign-extended to SEW before comparison.

With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.

FAQ

How does VMAXU.VX differ from the signed form?