Select the smaller value element by signed integer ordering and write the selected SEW-bit pattern to vd.
VMIN.VX is the RISC-V V extension vector-scalar signed minimum instruction. Each active body element reads vs2[i] and integer scalar x[rs1], compares them by signed integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
Starts from OP-V encoding fields, then shows how VMIN compares active elements as signed integers and writes the smaller SEW-bit pattern to vd.
Require valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. An ordinary masked vd cannot be v0; v0 cannot supply both mask and SEW data. Same-width source/destination overlap is legal.
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
vmin.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed minimum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
VMIN.VX writes the smaller SEW-bit pattern from vs2[i] and x[rs1] after the XLEN/SEW rule to vd[i] for active body elements, using signed ordering.
Compare vs2[i] with x[rs1] after the XLEN/SEW rule in SEW-wide two's-complement signed order; write the smaller source bits to vd[i]. This sets neither vxsat nor fflags.
32-bit OP-V: opcode=1010111, funct6=000101, funct3=100. [, v0.t] is optional: omitted means vm=1; included means vm=0.
rs1 selects an integer register. XLEN>SEW uses low SEW bits; XLEN<SEW sign-extends, including for VMINU.
Require V 1.0, valid vtype, enabled VS, and supported SEW. Body is vstart≤i<vl; prestart is unchanged. Inactive elements follow vma; tails follow vta. vl=0 or vstart≥vl updates no destination, including tails. The animation fixes m1, VLEN=4096, and vstart=0; steps are not processor cycles.
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], x11=3, v0.mask=[1,0,1,1] → v4=[0xffffffff,policy,0x80000000,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, ta/ma, and initialized sources; v0.t used; v8=[0xffffffff,2,0x80000000,7], x11=3, v0.mask=[1,0,1,1] → v4=[0xffffffff,policy,0x80000000,3]. policy retains the old value or writes all ones; tails are not guaranteed zero.
VMIN.VX uses signed integer ordering; the corresponding U form uses unsigned integer ordering. Both write back the selected source's SEW-bit pattern; the .vx scalar source first follows the XLEN/SEW scalar rule.
VMIN.VX compares and selects source bits; it neither sets vxsat or fflags nor clears existing flags. This does not rule out exceptions for invalid vtype, disabled VS, or reserved encodings.
With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.