How does VFNCVT differ from VFWCVT?
VFNCVT narrows from 2*SEW source elements to SEW destination elements; VFWCVT widens from SEW source elements to 2*SEW destination elements. The direction, register-group size, and allowed overlap rules differ.
VFNCVT.XU.F.W
RISC-V VFNCVT.XU.F.W Instruction Details
Instruction ManualOPFVVNarrow 2*SEW FP source elements to SEW unsigned integers using frm rounding.
Instruction Syntax
vfncvt.xu.f.w vd, vs2[, v0.t]
Operand Breakdown
Syntax is vd, vs2[, v0.t]; vs1=10000 is a VFUNARY0 selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; .w does not mean a fixed 32-bit width.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
FP-to-integer conversion rounds by dynamic frm before checking the SEW destination range. Overflow, infinity, and NaN clip under scalar conversion rules and raise NV; changed values raise NX only without NV. A negative fraction rounded to 0 can be a valid unsigned conversion. The animation accepts only finite binary64 inputs whose result fits 32 bits and does not display fflags.
V 1.0 supports this 64-to-32 path on RV32/RV64 and depends on F/D. This conversion at SEW=16 requires Zvfh; Zvfh also defines the SEW=8 binary16-to-8-bit-integer path. The animation fixes SEW=32, LMUL=m1, VLEN=4096, and vstart=0.
Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
VVector Type ConvertFloating-Point
Instruction Behavior
VFNCVT.XU.F.W converts EEW=2*SEW FP elements in vs2 to SEW-bit unsigned integers in vd using dynamic frm. Unrepresentable rounded results clip under scalar conversion rules and raise NV; otherwise a changed value raises NX. Only active elements execute; no integer GPR is written.
VFNCVT.XU.F.W Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 narrowing conversion lane by lane: each active lane converts the 2*SEW FP value in vs2[i] to an unsigned integer.
Instruction input
vfncvt.xu.f.w
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
source EEWsource element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x48881257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
10000
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: narrow_round.frm_unsigned(0.25) -> 0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
narrow_round.frm_unsigned(0.25)
0
i=1active
narrow_round.frm_unsigned(1.5)
2
i=2skip
v0.t=0, not executed
--
i=3active
narrow_round.frm_unsigned(3.75)
4
i=4active
narrow_round.frm_unsigned(7.125)
7
i=5active
narrow_round.frm_unsigned(8.5)
8
i=6skip
v0.t=0, not executed
--
i=7active
narrow_round.frm_unsigned(31.25)
31
source EEW=64 / binary64 -> destination width=32: round by dynamic frm (RNE, RTZ, RDN, RUP, or RMM), then check the 32-bit unsigned integer range. Reserved frm rejects encoding and execution. This model accepts only finite inputs whose rounded result is in range; NaN, infinity, overflow clipping, and fflags follow the official RVV/scalar FP rules and are outside this teaching computation.
The teaching context fixes VLEN=4096, LMUL=m1, SEW=32, vstart=0, valid vtype, enabled VS/FS, and valid frm. The source is an even vs2..vs2+1 group and the destination is one register; overlap must start at the source group's lowest register and forces mask/tail agnostic. VL=0 updates no destination elements, including tails. Inactive and tail values remain unspecified in this display; full fflags are not modeled. NaNs, infinities, and out-of-range integer conversions are legal FP inputs outside this model, not illegal instructions.
Quick Understanding & Search Notes
Read it as a 2*SEW FP to SEW unsigned-integer narrowing conversion, then check that rounding comes from frm.
VFNCVT.XU.F.W uses the RVV VFUNARY0 conversion encoding space: selector(vs1[19:15])=10000, funct6=010010, funct3=001 (OPFVV), and opcode=1010111 (OP-V). This vs1 field is an encoding selector, not a source register in the assembly syntax.
This family is narrowing: the vs2 source elements are 2*SEW wide and the vd destination elements are SEW wide; it is not single-width VFCVT or widening VFWCVT.
The narrowing source register group has twice the destination EMUL; by the official narrowing overlap rule, if the destination group overlaps the source group, the destination group's lowest-numbered register must equal the source group's lowest-numbered register.
Only active elements within vl execute; with vm=0, v0.t controls activity, and inactive/tail elements follow the current vma/vta policy.
Ordinary FP conversions use frm; rtz/rod forms have instruction-specified result rounding, while frm validity still follows the official vector FP rules; these conversions do not use fixed-point vxrm.
Vector Execution Context
Syntax is vd, vs2[, v0.t]; vs1=10000 is a VFUNARY0 selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; .w does not mean a fixed 32-bit width.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
FP-to-integer conversion rounds by dynamic frm before checking the SEW destination range. Overflow, infinity, and NaN clip under scalar conversion rules and raise NV; changed values raise NX only without NV. A negative fraction rounded to 0 can be a valid unsigned conversion. The animation accepts only finite binary64 inputs whose result fits 32 bits and does not display fflags.
V 1.0 supports this 64-to-32 path on RV32/RV64 and depends on F/D. This conversion at SEW=16 requires Zvfh; Zvfh also defines the SEW=8 binary16-to-8-bit-integer path. The animation fixes SEW=32, LMUL=m1, VLEN=4096, and vstart=0.
Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
Common Usage Scenarios
Store wide FP results as narrower unsigned integers
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. The source group is v2/v3 with EEW=64. Omitting v0.t makes the example unmasked: binary64 v2=[-0.25,0.25,1.5,2.5] → uint32 v1=[0,0,2,2] (NX). Tails follow ta without assumed zeroing.
Vectorized format compaction
Assume V/VS/FS enabled, valid vtype, frm=RNE, supported e32,m1 and required FP formats, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. The source group is v2/v3 with EEW=64. Omitting v0.t makes the example unmasked: binary64 v2=[-0.25,0.25,1.5,2.5] → uint32 v1=[0,0,2,2] (NX). Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax is vd, vs2[, v0.t]; vs1=10000 is a VFUNARY0 selector, not a second source. funct6=010010, funct3=001, opcode=1010111; the instruction is 32 bits.
- Source EEW=2*SEW, EMUL=2*LMUL; destination EEW=SEW, EMUL=LMUL. Groups are at most eight registers and align to their size. Overlap must start at the same lowest register and forces mask/tail agnostic; .w does not mean a fixed 32-bit width.
Semantic Check
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. Masked vd cannot overlap v0; data sources cannot read v0 at both data EEW and mask EEW=1.
- Prestart is unchanged. At vl=0 or vstart≥vl no destination elements change, including tails. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- FP-to-integer conversion rounds by dynamic frm before checking the SEW destination range. Overflow, infinity, and NaN clip under scalar conversion rules and raise NV; changed values raise NX only without NV. A negative fraction rounded to 0 can be a valid unsigned conversion. The animation accepts only finite binary64 inputs whose result fits 32 bits and does not display fflags.
- V 1.0 supports this 64-to-32 path on RV32/RV64 and depends on F/D. This conversion at SEW=16 requires Zvfh; Zvfh also defines the SEW=8 binary16-to-8-bit-integer path. The animation fixes SEW=32, LMUL=m1, VLEN=4096, and vstart=0.
- Valid vtype, supported FP widths, and enabled VS/FS are required; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0 or with no active elements. vxrm does not control FP operations. Teaching steps are not processor cycles.
Pitfalls / Common Confusions
Negative, NaN, infinity, and out-of-range inputs follow the official FP conversion result and exception rules; do not treat this as plain truncation.
This form uses dynamic frm; use vfncvt.rtz.xu.f.w for fixed round-toward-zero.
FAQ
Does VFNCVT use vxrm for rounding?
No. VFNCVT is a floating-point/integer conversion family: ordinary forms use floating-point frm, while rtz and rod are instruction-specified fixed rounding forms. vxrm is for fixed-point rounding instructions.
How are NaNs, infinities, and negative inputs converted?
The destination range is 0..2^SEW−1. A negative out-of-range rounded result or −∞ yields 0; positive overflow, +∞, or NaN yields 2^SEW−1, raising NV. A negative fraction rounded to 0 is valid and raises NX when its value changes.