How is VFWCVT.XU.F.V different from VFCVT?
VFWCVT.XU.F.V is a VFWCVT widening form: the source is SEW and the destination is 2*SEW. Single-width VFCVT uses the current SEW for both source and destination.
VFWCVT.XU.F.V
RISC-V VFWCVT.XU.F.V Instruction Details
Instruction ManualOPFVVVFWCVT.XU.F.V widens each active vs2[i] from an SEW-wide FP value to a 2*SEW-wide unsigned integer result and writes vd[i].
Instruction Syntax
vfwcvt.xu.f.v vd, vs2, vm
Operand Breakdown
Syntax: vfwcvt.xu.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01000 is a fixed VFUNARY0 selector, not a second vector source.
Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic.
Convert the FP source to a double-width unsigned integer under dynamic frm. Check the integer range after rounding. NaNs, infinities, or out-of-range results raise NV and clip by scalar-conversion rules; inexact results raise NX when NV is not raised.
Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
VVector Type ConvertFloating-Point
Instruction Behavior
VFWCVT.XU.F.V is a RISC-V V-extension VFWCVT widening floating-point/integer conversion instruction with syntax vfwcvt.xu.f.v vd, vs2, vm. It executes only for active elements within vl, uses the current SEW for source elements, and writes 2*SEW-wide destination elements; on the base V FP32/FP64 path, this page animation demonstrates SEW=32 inputs producing 64-bit destination results. The encoding uses OP-V, funct6=010010, funct3=001, and VFUNARY0 vs1 selector 01000. When rounding is required, the floating-point dynamic rounding mode frm is used; this page animation uses RNE as a checkable example; vm=0 uses v0.t as the execution mask and vm=1 is unmasked.
VFWCVT.XU.F.V Decode And Execute Animation
Decode the OP-V encoding and execute a VFUNARY0 widening conversion lane by lane: each active lane converts the FP value in vs2[i] to a double-width unsigned integer.
Instruction input
vfwcvt.xu.f.v
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
dest EEWdestination element width
vta/vmatail/inactive policy
opcodeOP-V major opcode
vs1VFUNARY0 conversion selector
Encoding fields
0x48841257
31..26
25
24..20
19..15
14..12
11..7
6..0
010010
funct6
0
vm
01000
vs2
01000
vs1/sel
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: widen_round.frm_unsigned(0.25) -> 0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
widen_round.frm_unsigned(0.25)
0
i=1active
widen_round.frm_unsigned(1.5)
2
i=2skip
v0.t=0, not executed
--
i=3active
widen_round.frm_unsigned(3.75)
4
i=4active
widen_round.frm_unsigned(7.125)
7
i=5active
widen_round.frm_unsigned(8.5)
8
i=6skip
v0.t=0, not executed
--
i=7active
widen_round.frm_unsigned(31.25)
31
This model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, valid vtype, enabled VS/FS, and ta/ma. The source is represented as binary32 before selected dynamic frm rounding; the 64-bit integer demo displays results only within ±(2^53−1), with a lower bound of 0 for unsigned forms. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model; the real instruction still handles these conditions by the official FP rules.
Quick Understanding & Search Notes
VFWCVT.XU.F.V is best understood as a VFUNARY0 widening conversion: after decoding vs1=01000, active elements convert vs2[i] from an SEW-wide FP value to a 2*SEW-wide unsigned integer result.
In the OP-V encoding, funct6=010010 and funct3=001 select the vector FP/integer conversion group, and VFUNARY0 vs1=01000 selects VFWCVT.XU.F.V.
Syntax operands are vd, vs2, and optional v0.t (vm); VL, SEW, frm, v0 mask bits, and source element values are execution context.
This is a widening conversion: source elements use the current SEW and destination elements use 2*SEW; the common base-V path is SEW=32 input producing a 64-bit destination result.
When rounding is required, the floating-point dynamic rounding mode frm is used; this page animation uses RNE as a checkable example.
Only active elements within vl execute; vm=0 uses v0.t and vm=1 is unmasked.
Widening instructions obey the official widening register-overlap constraints; this page animation uses an even vd to represent the vd..vd+1 destination group for LMUL=1.
For FP-to-integer conversion, the valid input range is judged after rounding; NaNs, infinities, out-of-range cases, and inexact/invalid flags follow the official RVV and scalar FP conversion rules.
The animation represents inputs as binary32 before integer rounding; values outside its demo range do not produce an encoding or result.
Vector Execution Context
Syntax: vfwcvt.xu.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01000 is a fixed VFUNARY0 selector, not a second vector source.
Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic.
Convert the FP source to a double-width unsigned integer under dynamic frm. Check the integer range after rounding. NaNs, infinities, or out-of-range results raise NV and clip by scalar-conversion rules; inexact results raise NX when NV is not raised.
Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
Common Usage Scenarios
SEW FP to 2*SEW integers
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omitting v0.t makes this unmasked: v4(binary32)=[2.5,3.5,0,1.75] → v2/v3(uint64)=[2,4,0,2]. Tails follow ta without guaranteed zeros.
active-element type conversion
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omitting v0.t makes this unmasked: v4(binary32)=[2.5,3.5,0,1.75] → v2/v3(uint64)=[2,4,0,2]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwcvt.xu.f.v vd, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=010010. vs1=01000 is a fixed VFUNARY0 selector, not a second vector source.
- Narrow vector sources have EEW=SEW, EMUL=LMUL; vd has EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Narrow-source/wide-destination overlap requires source EMUL≥1 and equal highest register numbers; legal different-EEW overlap forces mask/tail agnostic.
Semantic Check
- Convert the FP source to a double-width unsigned integer under dynamic frm. Check the integer range after rounding. NaNs, infinities, or out-of-range results raise NV and clip by scalar-conversion rules; inexact results raise NX when NV is not raised.
- Omitting v0.t means vm=1; including it means vm=0. Active elements satisfy vstart≤i<vl with the mask enabled; only active-element exceptions accrue in fflags. A masked destination cannot include v0; one register cannot be read as data and mask sources with different EEWs.
- Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl no destination elements, including tails, update. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Every vector FP instruction requires valid frm, even without frm-based rounding or at vl=0; invalid frm use is reserved. vxrm is not used. This finite teaching model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and ta/ma; it is not a complete FP simulator.
Pitfalls / Common Confusions
This is a widening VFWCVT form: the source is SEW and the destination is 2*SEW; do not treat it as single-width VFCVT or narrowing VFNCVT.
At LMUL=m1, the destination has EMUL=2 and vd must be even; a narrow source may overlap only the highest-numbered register of that destination group.
With vm=0, v0.t selects active elements only; masked-off elements do not produce the conversion result shown by the animation.
For FP-to-integer conversion, the valid domain is judged after rounding; NaNs, infinities, out-of-range cases, invalid, and inexact still follow the official FP conversion rules.
This animation fixes SEW=32, converting binary32 sources to 64-bit integers; displayed results are restricted to the safe-integer demo range.
FAQ
Where does VFWCVT.XU.F.V take its rounding mode from?
When rounding is required, it uses the floating-point dynamic rounding mode frm, not the fixed-point vxrm.
How does VFWCVT.XU.F.V use the mask operand?
vm=0 converts only active elements with v0[i]=1; vm=1 is unmasked. Inactive/tail elements follow vma/vta, with legal different-EEW overlap forcing agnostic. At vl=0 or vstart≥vl no destination elements update.
Why does this page animation expose only SEW=32?
This model fixes SEW=32 and shows binary32-to-64-bit-integer widening conversion; it does not simulate every optional FP format.