VFNCVTBF16.F.F.W

RISC-V VFNCVTBF16.F.F.W Instruction Details

Instruction ManualOPFVV

Narrow FP32 vector sources to BF16 using frm rounding.

Instruction Syntax

vfncvtbf16.f.f.w vd, vs2, vm

Syntax: vfncvtbf16.f.f.w vd, vs2[, v0.t]; vd and vs2 select the lowest v0–v31 register in each vector group. No FP scalar source or immediate.

32-bit OP-V: funct6=010010, bits19:15=11101 (fixed VFUNARY0 selector), funct3=001, opcode=1010111. vm=0 uses v0.t; omitting it means vm=1.

Requires Zvfbfmin (depends on Zve32f), enabled vector/FP state and valid vtype; only SEW=16 is legal. vs2 supplies FP32 at EEW=32, EMUL=2*LMUL; vd receives BF16 at EEW=16, EMUL=LMUL, rounded by frm.

Group starts align to EMUL, with EMUL<=8. Narrowing overlap shares the lowest register; widening overlap needs source EMUL>=1 and a shared highest register. Masked vd excludes v0; v0 cannot supply mask and data together. Legal different-EEW overlap forces mask/tail agnostic.

Only mask-enabled vstart<=i<vl elements execute. Inactive/tail policies do not guarantee zeroing. vstart>=vl (including vl=0) updates no destination elements. Invalid frm use is always reserved, even for exact conversion or no active elements.

ZvfbfminVector Operations

Related Search Terms

vfncvtbf16.f.f.w instruction RISC-V BF16 convert FP32 to BF16 vfncvtbf16 encoding Zvfbfmin instruction BF16 vector narrowing RISC-V frm rounding

Instruction Behavior

VFNCVTBF16.F.F.W, with SEW=16, narrows 32-bit FP32 source elements from vs2 to 16-bit BF16 results in vd. The conversion rounds according to frm and may raise Overflow, Underflow, Inexact, or Invalid; it belongs to Zvfbfmin.

VFNCVTBF16.F.F.W Decode And Execute Animation

Decode the OP-V encoding and execute vector BF16 narrowing conversion: each active lane rounds an FP32 source value to BF16 using frm.

Instruction input

vfncvtbf16.f.f.w

vdUse v0-v31vs2Use v0-v31vmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX256maximum element count at m1

vstart0prestart elements are outside this animation

frm

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

source EEW32source element width

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vs2 elementsComma-separated finite values or 8-digit 0x bit patterns, count must equal VL

vs111101VFUNARY0 conversion selector

v0 mask bits0/1 string, length must equal VL

Encoding fields

0x488e9257

31..26

24..20

19..15

14..12

11..7

6..0

010010

funct6

01000

vs2

11101

vs1/sel

001

funct3

00100

1010111

OP-V

Execution data path

lane 0: bf16_rne(1.5) -> 0x3fc0 (1.5)

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

bf16_rne(1.5)

0x3fc0 (1.5)

i=1active

bf16_rne(-2.25)

0xc010 (-2.25)

i=2skip

v0.t=0, not executed

i=3active

bf16_rne(-4.5)

0xc090 (-4.5)

i=4active

bf16_rne(7.75)

0x40f8 (7.75)

i=5active

bf16_rne(-8.25)

0xc104 (-8.25)

i=6skip

v0.t=0, not executed

i=7active

bf16_rne(-31.25)

0xc1fa (-31.25)

The teaching context fixes SEW=16, LMUL=m1, VLEN=4096, VLMAX=256, vstart=0, valid vtype, enabled VS/FS, and valid frm. The FP32 source is an even vs2..vs2+1 group and the BF16 destination is one register; legal overlap starts at the lowest source register. Numeric inputs are first represented as FP32, then narrowed by the selected frm. Legal different-EEW overlap forces mask/tail agnostic. Inactive/tail values are not specified by this display; VL=0 updates no destination elements. NaNs, infinities, fflags, and processor cycles are outside this model. A result outside the finite demo range is a model limitation, not an illegal instruction.

SEW=16, source EEW=32 / FP32 -> destination EEW=16 / BF16. The animation demonstrates finite BF16 results rounded by the selected frm; officially this instruction rounds by frm and may set Overflow, Underflow, Inexact, and Invalid.

Quick Understanding & Search Notes

This is the RVV BF16 FP32-to-BF16 narrowing conversion: the assembly syntax has only vd, vs2, and vm; SEW is fixed to 16, and vs1[19:15]=11101 is a VFUNARY0 selector, not a source register.

OP-V encoding: funct6=010010, vs1/selector=11101, funct3=001 (OPFVV), opcode=1010111.

Official reserved encoding: any SEW value other than 16 is reserved.

Source elements are EEW=32 FP32 and destination elements are EEW=16 BF16; active elements are controlled by vl and v0.t.

The result rounds according to frm, with Overflow, Underflow, Inexact, and Invalid exceptions.

The animation demonstrates selected frm rounding with finite FP32 examples; NaNs, infinities, and fflags are outside its computation.

With vm=0, only body elements enabled by v0.t execute; omitting the mask operand means vm=1. vl=0 updates no destination elements.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §25 BF16 The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §31 V

Vector Execution Context

Body elements satisfy vstart<=i<vl; only mask-enabled elements perform the conversion. At vstart>=vl (including vl=0), all destination elements remain unchanged. SEW is fixed to 16; LMUL determines register-group sizes, while vta/vma govern tail/inactive policy.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Vector Operations

Enable Zvfbfmin and vector/FP state, with SEW=16, LMUL=m1, VLEN=128, vl=1, vstart=0, frm=RNE and no mask: v8[0]=1.5 (FP32 0x3FC00000) → v4[0]=BF16 0x3FC0; remaining destination elements follow tail policy.

Machine Learning

Pre-Use Checklist

Syntax Check

Syntax: vfncvtbf16.f.f.w vd, vs2[, v0.t]; vd and vs2 select the lowest v0–v31 register in each vector group. No FP scalar source or immediate.
32-bit OP-V: funct6=010010, bits19:15=11101 (fixed VFUNARY0 selector), funct3=001, opcode=1010111. vm=0 uses v0.t; omitting it means vm=1.

Semantic Check

Requires Zvfbfmin (depends on Zve32f), enabled vector/FP state and valid vtype; only SEW=16 is legal. vs2 supplies FP32 at EEW=32, EMUL=2*LMUL; vd receives BF16 at EEW=16, EMUL=LMUL, rounded by frm.
Group starts align to EMUL, with EMUL<=8. Narrowing overlap shares the lowest register; widening overlap needs source EMUL>=1 and a shared highest register. Masked vd excludes v0; v0 cannot supply mask and data together. Legal different-EEW overlap forces mask/tail agnostic.
Only mask-enabled vstart<=i<vl elements execute. Inactive/tail policies do not guarantee zeroing. vstart>=vl (including vl=0) updates no destination elements. Invalid frm use is always reserved, even for exact conversion or no active elements.

Pitfalls / Common Confusions

SEW must be 16; other SEW encodings are reserved.

The vs2 source elements have EEW=32 FP32, while vd destination elements have EEW=16 BF16.

Narrowing to BF16 rounds according to frm; it is not just taking the upper 16 FP32 bits.

BF16 has only 7 fraction bits, so the result is much less precise than FP32.

NaN, infinity, overflow, underflow, and exception flags follow the official BF16/FP conversion rules.

FAQ

Do these vector BF16 instructions support any SEW?

No. The official vector BF16 instructions reserve encodings when SEW is not 16; this page animation fixes SEW=16.

Is BF16 the same as IEEE binary16?

No. BF16 has 1 sign bit, 8 exponent bits, and 7 fraction bits; it differs from half-precision binary16 in exponent and fraction widths.

Is VFNCVTBF16.F.F.W just truncating FP32?

No. The official semantics are FP32-to-BF16 narrowing conversion rounded by frm; simple truncation would misrepresent rounding and exception boundaries.