Does FCVT.BF16.S imply BF16 add/sub/mul/div support?
No. Zfbfmin/Zvfbfmin mainly provide BF16/FP32 conversion; Zvfbfwma provides widening multiply-accumulate.
FCVT.BF16.S
RISC-V FCVT.BF16.S Instruction Details
Instruction ManualR-typeNarrow FP32 to BF16, rounded by rm/frm.
Instruction Syntax
fcvt.bf16.s rd, rs1[, rm]
Syntax: fcvt.bf16.s rd, rs1[, rm]; both rd and rs1 select FP f0–f31, including readable/writable f0. rs2 is a fixed format selector, not a second source.
32-bit OP-FP: funct5=01000, fmt=10, rs2=01000, funct3=rm, opcode=1010011; no immediate.
RV32/RV64 Zfbfmin 1.0 requires F; enable the extensions and FP state. Round using rm; rm=111 selects frm. OF/UF/NX/NV may accrue. Optional rm defaults to dyn in assembly; static rm=101/110 and dynamic frm=101–111 follow reserved-encoding rules.
Subnormals are supported. Sources narrower than FLEN require valid NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get upper ones. sNaN adds NV and NaN results are canonical; flags accrue without clearing prior flags or themselves causing FP traps.
ZfbfminFloating-Point Convert
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FCVT.BF16.S uses opcode 1010011 (0x53), funct7 0100010, rs2 fixed 8 (BF16.S). 32-bit OP-FP: funct5=01000, fmt=10, rs2=01000, funct3=rm, opcode=1010011; no immediate.
Format: OP-FP BF16 conversion fields (fmt=10, rs2=01000)
opcode: 1010011 (0x53)
funct7: 0100010 (0x22)
rs2: fixed 8 (BF16.S)
Instruction Behavior
FCVT.BF16.S (Zfbfmin, depending on F) narrows the single-precision FP32 value in f[rs1] to BF16, rounded according to the instruction's encoded rm field, and writes the BF16 result to f[rd] with the normal NaN-boxing behavior for a narrower floating-point result. It is a minimal FP32/BF16 conversion instruction and does not provide native BF16 arithmetic. It may set Overflow, Underflow, Inexact, and Invalid exception flags.
Quick Understanding & Search Notes
FCVT.BF16.S belongs to the RISC-V BF16 extensions; BF16 is a 16-bit FP format with 1 sign bit, 8 exponent bits, and 7 fraction bits.
Narrowing to BF16 rounds and may set OF/UF/NX/NV.
BF16 scalar inputs/results follow RISC-V NaN-boxing rules.
Common Usage Scenarios
Convert FP32 data to BF16 interchange format
fcvt.bf16.s f0, f1, rne # boxed FP32 0x3F808000 (1.00390625) -> boxed BF16 0x3F80 (1.0), NX. Initialize the example source and enable the required extensions and state.
Pre-Use Checklist
Syntax Check
- Syntax: fcvt.bf16.s rd, rs1[, rm]; both rd and rs1 select FP f0–f31, including readable/writable f0. rs2 is a fixed format selector, not a second source.
- 32-bit OP-FP: funct5=01000, fmt=10, rs2=01000, funct3=rm, opcode=1010011; no immediate.
Semantic Check
- RV32/RV64 Zfbfmin 1.0 requires F; enable the extensions and FP state. Round using rm; rm=111 selects frm. OF/UF/NX/NV may accrue. Optional rm defaults to dyn in assembly; static rm=101/110 and dynamic frm=101–111 follow reserved-encoding rules.
- Subnormals are supported. Sources narrower than FLEN require valid NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get upper ones. sNaN adds NV and NaN results are canonical; flags accrue without clearing prior flags or themselves causing FP traps.
Pitfalls / Common Confusions
BF16 is a 16-bit format with 1 sign bit, 8 exponent bits, and 7 fraction bits (p=8); its range is close to FP32 but its precision is lower than FP16.
The conversion rounds according to rm; it is not just truncation of the upper 16 bits.
Zfbfmin only provides BF16/FP32 conversion plus reused FLH/FSH/FMV.H.X/FMV.X.H, not native BF16 arithmetic.
BF16 subnormals are fully supported by these extensions; exception flags follow normal RISC-V floating-point rules.
FAQ
Which registers hold the source and destination?
Both rd and rs1 select FP registers f0–f31; f0 is readable and writable. Sources narrower than FLEN are checked for NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get all upper bits set to one.