Does FCVT.BF16.S imply BF16 add/sub/mul/div support?
No. Zfbfmin/Zvfbfmin mainly provide BF16/FP32 conversion; Zvfbfwma provides widening multiply-accumulate.
FCVT.BF16.S
RISC-V FCVT.BF16.S Instruction Details
Instruction ManualR-typeNarrow FP32 to BF16, rounded by rm/frm.
Instruction Syntax
fcvt.bf16.s rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfbfminFloating-Point Convert
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FCVT-BF16-S uses opcode 1010011 (0x53), funct7 0100010, rs2 fixed 8 (BF16.S). The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: OP-FP BF16 conversion fields (fmt=10, rs2=01000)
opcode: 1010011 (0x53)
funct7: 0100010 (0x22)
rs2: fixed 8 (BF16.S)
Instruction Behavior
FCVT.BF16.S (Zfbfmin, depending on F) narrows the single-precision FP32 value in f[rs1] to BF16, rounded according to the instruction's encoded rm field, and writes the BF16 result to f[rd] with the normal NaN-boxing behavior for a narrower floating-point result. It is a minimal FP32/BF16 conversion instruction and does not provide native BF16 arithmetic. It may set Overflow, Underflow, Inexact, and Invalid exception flags.
Quick Understanding & Search Notes
FCVT.BF16.S belongs to the RISC-V BF16 extensions; BF16 is a 16-bit FP format with 1 sign bit, 8 exponent bits, and 7 fraction bits.
Narrowing to BF16 rounds and may set OF/UF/NX/NV.
BF16 scalar inputs/results follow RISC-V NaN-boxing rules.
Common Usage Scenarios
Deep learning inference
Understand this scenario with real code like «fcvt.bf16.s f0, f1 # f0 = bf16(f1), rounded according to the encoded rm field».
BF16 model deployment
Understand this scenario with real code like «fcvt.bf16.s f0, f1 # f0 = bf16(f1), rounded according to the encoded rm field».
Memory bandwidth reduction
Understand this scenario with real code like «fcvt.bf16.s f0, f1 # f0 = bf16(f1), rounded according to the encoded rm field».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
BF16 is a 16-bit format with 1 sign bit, 8 exponent bits, and 7 fraction bits (p=8); its range is close to FP32 but its precision is lower than FP16.
The conversion rounds according to rm; it is not just truncation of the upper 16 bits.
Zfbfmin only provides BF16/FP32 conversion plus reused FLH/FSH/FMV.H.X/FMV.X.H, not native BF16 arithmetic.
BF16 subnormals are fully supported by these extensions; exception flags follow normal RISC-V floating-point rules.
FAQ
What is the SEW restriction for FCVT.BF16.S?
The scalar form does not use V SEW; it operates on BF16/FP32 scalar values in FP registers.