Does FCVT.S.BF16 imply BF16 add/sub/mul/div support?
No. Zfbfmin/Zvfbfmin mainly provide BF16/FP32 conversion; Zvfbfwma provides widening multiply-accumulate.
FCVT.S.BF16
RISC-V FCVT.S.BF16 Instruction Details
Instruction ManualR-typeExactly widen BF16 to FP32.
Instruction Syntax
fcvt.s.bf16 rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZfbfminFloating-Point Convert
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FCVT-S-BF16 uses opcode 1010011 (0x53), funct7 0100000, rs2 fixed 6 (BF16). The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: OP-FP BF16 conversion fields (fmt=00, rs2=00110)
opcode: 1010011 (0x53)
funct7: 0100000 (0x20)
rs2: fixed 6 (BF16)
Instruction Behavior
FCVT.S.BF16 (Zfbfmin, depending on F) exactly widens the NaN-boxed BF16 value in f[rs1] to single-precision FP32 and writes it to f[rd]. For normal values or infinity, the BF16 encoding is shifted left by 16 bits into the high half of the FP32 encoding and the low 16 fraction bits are zero-filled; the FP32 result is NaN-boxed in wider FLEN registers. The conversion needs no rounding, but inputs such as signaling NaNs may set Invalid.
Quick Understanding & Search Notes
FCVT.S.BF16 belongs to the RISC-V BF16 extensions; BF16 is a 16-bit FP format with 1 sign bit, 8 exponent bits, and 7 fraction bits.
Widening to FP32 is exact; normal/infinity inputs are shifted into the FP32 encoding and zero-filled.
BF16 scalar inputs/results follow RISC-V NaN-boxing rules.
Common Usage Scenarios
BF16 type promotion
Understand this scenario with real code like «fcvt.s.bf16 f0, f1 # f0 = fp32(f1[bf16]), exact».
BF16↔FP32 interop
Understand this scenario with real code like «fcvt.s.bf16 f0, f1 # f0 = fp32(f1[bf16]), exact».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
This is an exact widening conversion and does not use a rounding mode; assembly normally omits rm.
The source BF16 scalar must be correctly NaN-boxed as a narrower FP value; otherwise it is treated as canonical NaN input.
The result is FP32 and is NaN-boxed in the floating-point register when FLEN>32.
Widening BF16 to FP32 is exact and does not use a rounding mode.
FAQ
What is the SEW restriction for FCVT.S.BF16?
The scalar form does not use V SEW; it operates on BF16/FP32 scalar values in FP registers.