Does FCVT.S.BF16 imply BF16 add/sub/mul/div support?
No. Zfbfmin/Zvfbfmin mainly provide BF16/FP32 conversion; Zvfbfwma provides widening multiply-accumulate.
FCVT.S.BF16
RISC-V FCVT.S.BF16 Instruction Details
Instruction ManualR-typeExactly widen BF16 to FP32.
Instruction Syntax
fcvt.s.bf16 rd, rs1[, rm]
Syntax: fcvt.s.bf16 rd, rs1[, rm]; both rd and rs1 select FP f0–f31, including readable/writable f0. rs2 is a fixed format selector, not a second source.
32-bit OP-FP: funct5=01000, fmt=00, rs2=00110, funct3=rm, opcode=1010011; no immediate.
RV32/RV64 Zfbfmin 1.0 requires F; enable the extensions and FP state. Widening is exact and mathematically unaffected by rm; software should encode RNE (000). Only NV may be added. Optional rm defaults to dyn in assembly; static rm=101/110 and dynamic frm=101–111 follow reserved-encoding rules.
Subnormals are supported. Sources narrower than FLEN require valid NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get upper ones. sNaN adds NV and NaN results are canonical; flags accrue without clearing prior flags or themselves causing FP traps.
ZfbfminFloating-Point Convert
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FCVT.S.BF16 uses opcode 1010011 (0x53), funct7 0100000, rs2 fixed 6 (BF16). 32-bit OP-FP: funct5=01000, fmt=00, rs2=00110, funct3=rm, opcode=1010011; no immediate.
Format: OP-FP BF16 conversion fields (fmt=00, rs2=00110)
opcode: 1010011 (0x53)
funct7: 0100000 (0x20)
rs2: fixed 6 (BF16)
Instruction Behavior
FCVT.S.BF16 (Zfbfmin, depending on F) exactly widens the NaN-boxed BF16 value in f[rs1] to single-precision FP32 and writes it to f[rd]. For normal values or infinity, the BF16 encoding is shifted left by 16 bits into the high half of the FP32 encoding and the low 16 fraction bits are zero-filled; the FP32 result is NaN-boxed in wider FLEN registers. The conversion needs no rounding, but inputs such as signaling NaNs may set Invalid.
Quick Understanding & Search Notes
FCVT.S.BF16 belongs to the RISC-V BF16 extensions; BF16 is a 16-bit FP format with 1 sign bit, 8 exponent bits, and 7 fraction bits.
Widening to FP32 is exact; normal/infinity inputs are shifted into the FP32 encoding and zero-filled.
BF16 scalar inputs/results follow RISC-V NaN-boxing rules.
Common Usage Scenarios
Widen BF16 data to FP32
fcvt.s.bf16 f0, f1, rne # boxed BF16 0x3FC0 (1.5) -> FP32 0x3FC00000 (1.5). Initialize the example source and enable the required extensions and state.
Pre-Use Checklist
Syntax Check
- Syntax: fcvt.s.bf16 rd, rs1[, rm]; both rd and rs1 select FP f0–f31, including readable/writable f0. rs2 is a fixed format selector, not a second source.
- 32-bit OP-FP: funct5=01000, fmt=00, rs2=00110, funct3=rm, opcode=1010011; no immediate.
Semantic Check
- RV32/RV64 Zfbfmin 1.0 requires F; enable the extensions and FP state. Widening is exact and mathematically unaffected by rm; software should encode RNE (000). Only NV may be added. Optional rm defaults to dyn in assembly; static rm=101/110 and dynamic frm=101–111 follow reserved-encoding rules.
- Subnormals are supported. Sources narrower than FLEN require valid NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get upper ones. sNaN adds NV and NaN results are canonical; flags accrue without clearing prior flags or themselves causing FP traps.
Pitfalls / Common Confusions
The exact result is unaffected by rounding, but rm still exists: software should encode RNE (000), with normal legal/reserved encoding rules.
The source BF16 scalar must be correctly NaN-boxed as a narrower FP value; otherwise it is treated as canonical NaN input.
The result is FP32 and is NaN-boxed in the floating-point register when FLEN>32.
FAQ
Which registers hold the source and destination?
Both rd and rs1 select FP registers f0–f31; f0 is readable and writable. Sources narrower than FLEN are checked for NaN-boxing; malformed boxes become canonical quiet NaN. Narrower results get all upper bits set to one.