RISC-V FCVT.S.BF16 Instruction Details

Instruction ManualR-type

Exactly widen BF16 to FP32.

Instruction Syntax

fcvt.s.bf16 rd, rs1

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

ZfbfminFloating-Point Convert

Related Search Terms

fcvt.s.bf16 instruction RISC-V fcvt.s.bf16 fcvt.s.bf16 syntax fcvt.s.bf16 encoding fcvt.s.bf16 BF16 to FP32 convert fcvt.s.bf16 BF16 fcvt.s.bf16 BFloat16

Instruction Behavior

FCVT.S.BF16 (Zfbfmin, depending on F) exactly widens the NaN-boxed BF16 value in f[rs1] to single-precision FP32 and writes it to f[rd]. For normal values or infinity, the BF16 encoding is shifted left by 16 bits into the high half of the FP32 encoding and the low 16 fraction bits are zero-filled; the FP32 result is NaN-boxed in wider FLEN registers. The conversion needs no rounding, but inputs such as signaling NaNs may set Invalid.

Quick Understanding & Search Notes

FCVT.S.BF16 belongs to the RISC-V BF16 extensions; BF16 is a 16-bit FP format with 1 sign bit, 8 exponent bits, and 7 fraction bits.

Widening to FP32 is exact; normal/infinity inputs are shifted into the FP32 encoding and zero-filled.

BF16 scalar inputs/results follow RISC-V NaN-boxing rules.

RISC-V Unprivileged ISA Manual: BF16 extensions

Common Usage Scenarios

BF16 type promotion

Understand this scenario with real code like «fcvt.s.bf16 f0, f1 # f0 = fp32(f1[bf16]), exact».

BF16↔FP32 interop

Understand this scenario with real code like «fcvt.s.bf16 f0, f1 # f0 = fp32(f1[bf16]), exact».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is an exact widening conversion and does not use a rounding mode; assembly normally omits rm.

The source BF16 scalar must be correctly NaN-boxed as a narrower FP value; otherwise it is treated as canonical NaN input.

The result is FP32 and is NaN-boxed in the floating-point register when FLEN>32.

Widening BF16 to FP32 is exact and does not use a rounding mode.

FAQ

Does FCVT.S.BF16 imply BF16 add/sub/mul/div support?

No. Zfbfmin/Zvfbfmin mainly provide BF16/FP32 conversion; Zvfbfwma provides widening multiply-accumulate.

What is the SEW restriction for FCVT.S.BF16?

The scalar form does not use V SEW; it operates on BF16/FP32 scalar values in FP registers.