VFWCVTBF16.F.F.V

RISC-V VFWCVTBF16.F.F.V Instruction Details

Instruction ManualOPFVV

Exactly widen BF16 vector sources to FP32.

Instruction Syntax

vfwcvtbf16.f.f.v vd, vs2, vm

Syntax: vfwcvtbf16.f.f.v vd, vs2[, v0.t]; vd and vs2 select the lowest v0–v31 register in each vector group. No FP scalar source or immediate.

32-bit OP-V: funct6=010010, bits19:15=01101 (fixed VFUNARY0 selector), funct3=001, opcode=1010111. vm=0 uses v0.t; omitting it means vm=1.

Requires Zvfbfmin (depends on Zve32f), enabled vector/FP state and valid vtype; only SEW=16 is legal. vs2 supplies BF16 at EEW=16, EMUL=LMUL; vd receives FP32 at EEW=32, EMUL=2*LMUL, exactly.

Group starts align to EMUL, with EMUL<=8. Narrowing overlap shares the lowest register; widening overlap needs source EMUL>=1 and a shared highest register. Masked vd excludes v0; v0 cannot supply mask and data together. Legal different-EEW overlap forces mask/tail agnostic.

Only mask-enabled vstart<=i<vl elements execute. Inactive/tail policies do not guarantee zeroing. vstart>=vl (including vl=0) updates no destination elements. Invalid frm use is always reserved, even for exact conversion or no active elements.

ZvfbfminVector Operations

Related Search Terms

vfwcvtbf16.f.f.v instruction RISC-V BF16 convert BF16 to FP32 vfwcvtbf16 encoding Zvfbfmin instruction BF16 vector widening BF16 bit layout

Instruction Behavior

VFWCVTBF16.F.F.V, with SEW=16, exactly widens 16-bit BF16 source elements from vs2 to 32-bit FP32 results in vd. For normal values and infinities, the BF16 encoding is shifted left by 16 and the low 16 FP32 bits are zero-filled; it belongs to Zvfbfmin.

VFWCVTBF16.F.F.V Decode And Execute Animation

Decode the OP-V encoding and execute vector BF16 widening conversion: each active lane exactly widens BF16 to FP32.

Instruction input

vfwcvtbf16.f.f.v

vdUse v0-v31vs2Use v0-v31vmexecution mask control

Execution context

VLSEW

LMULm1fixed register-group multiplier

VLEN4096fixed vector-register length (bits)

VLMAX256maximum element count at m1

vstart0prestart elements are outside this animation

frmRNEexact widening conversion; this context fixes valid frm=RNE

FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled

dest EEW32destination element width

vta/vmata, matail/inactive policy

opcode1010111OP-V major opcode

vs2 elementsComma-separated finite values or 4-digit 0x bit patterns, count must equal VL

vs101101VFUNARY0 conversion selector

v0 mask bits0/1 string, length must equal VL

Encoding fields

0x48869257

31..26

24..20

19..15

14..12

11..7

6..0

010010

funct6

01000

vs2

01101

vs1/sel

001

funct3

00100

1010111

OP-V

Execution data path

lane 0: fp32(0x3fc0) -> 1.5 / 0x3fc00000

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

fp32(0x3fc0)

1.5 / 0x3fc00000

i=1active

fp32(0xc010)

-2.25 / 0xc0100000

i=2skip

v0.t=0, not executed

i=3active

fp32(0xc0c0)

-6 / 0xc0c00000

i=4active

fp32(0x4100)

8 / 0x41000000

i=5active

fp32(0xc120)

-10 / 0xc1200000

i=6skip

v0.t=0, not executed

i=7active

fp32(0xc1a0)

-20 / 0xc1a00000

The teaching context fixes SEW=16, LMUL=m1, VLEN=4096, VLMAX=256, vstart=0, valid vtype, enabled VS/FS, and valid frm. The BF16 source is one register and the FP32 destination is an even vd..vd+1 group; legal overlap is at the destination group's high end. Numeric inputs are first represented as FP32, then as BF16 under RNE, and finally widened exactly; raw patterns directly supply BF16 bits. Legal different-EEW overlap forces mask/tail agnostic. Inactive/tail values are not specified by this display; VL=0 updates no destination elements. NaNs, infinities, fflags, and processor cycles are outside this model. A result outside the finite demo range is a model limitation, not an illegal instruction.

SEW=16, source EEW=16 / BF16 -> destination EEW=32 / FP32. BF16-to-FP32 is an exact widening conversion; for normal numbers and infinity, the BF16 encoding is shifted left by 16 and the low 16 bits are zero-filled.

Quick Understanding & Search Notes

This is the RVV BF16 BF16-to-FP32 exact widening conversion: the assembly syntax has only vd, vs2, and vm; SEW is fixed to 16, and vs1[19:15]=01101 is a VFUNARY0 selector.

OP-V encoding: funct6=010010, vs1/selector=01101, funct3=001 (OPFVV), opcode=1010111.

Official reserved encoding: any SEW value other than 16 is reserved.

Source elements are EEW=16 BF16 and destination elements are EEW=32 FP32; active elements are controlled by vl and v0.t.

The widening conversion is exact; normal values and infinities shift the BF16 encoding left by 16 and write zeroes into the low 16 FP32 bits.

The page animation shows the mapping from raw 16-bit BF16 patterns to FP32 values and 32-bit encodings.

With vm=0, only body elements enabled by v0.t execute; omitting the mask operand means vm=1. vl=0 updates no destination elements.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §25 BF16 The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §31 V

Vector Execution Context

Body elements satisfy vstart<=i<vl; only mask-enabled elements perform the conversion. At vstart>=vl (including vl=0), all destination elements remain unchanged. SEW is fixed to 16; LMUL determines register-group sizes, while vta/vma govern tail/inactive policy.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Vector Operations

Enable Zvfbfmin and vector/FP state, with SEW=16, LMUL=m1, VLEN=128, vl=1, vstart=0, frm=RNE and no mask: v8[0]=BF16 0x3FC0 → v4[0]=1.5 (FP32 0x3FC00000); remaining destination elements follow tail policy.

Machine Learning

Pre-Use Checklist

Syntax Check

Syntax: vfwcvtbf16.f.f.v vd, vs2[, v0.t]; vd and vs2 select the lowest v0–v31 register in each vector group. No FP scalar source or immediate.
32-bit OP-V: funct6=010010, bits19:15=01101 (fixed VFUNARY0 selector), funct3=001, opcode=1010111. vm=0 uses v0.t; omitting it means vm=1.

Semantic Check

Requires Zvfbfmin (depends on Zve32f), enabled vector/FP state and valid vtype; only SEW=16 is legal. vs2 supplies BF16 at EEW=16, EMUL=LMUL; vd receives FP32 at EEW=32, EMUL=2*LMUL, exactly.
Group starts align to EMUL, with EMUL<=8. Narrowing overlap shares the lowest register; widening overlap needs source EMUL>=1 and a shared highest register. Masked vd excludes v0; v0 cannot supply mask and data together. Legal different-EEW overlap forces mask/tail agnostic.
Only mask-enabled vstart<=i<vl elements execute. Inactive/tail policies do not guarantee zeroing. vstart>=vl (including vl=0) updates no destination elements. Invalid frm use is always reserved, even for exact conversion or no active elements.

Pitfalls / Common Confusions

SEW must be 16; other SEW encodings are reserved.

The vs2 source elements have EEW=16 BF16, while vd destination elements have EEW=32 FP32.

BF16-to-FP32 is an exact widening conversion and does not use frm rounding.

This instruction is a format conversion, not BF16 arithmetic.

Invalid may be set, for example for signaling NaN; exact widening of finite values, normals, subnormals, and infinity does not round and does not raise OF, UF, or NX.

FAQ

Do these vector BF16 instructions support any SEW?

No. The official vector BF16 instructions reserve encodings when SEW is not 16; this page animation fixes SEW=16.

Is BF16 the same as IEEE binary16?

No. BF16 has 1 sign bit, 8 exponent bits, and 7 fraction bits; it differs from half-precision binary16 in exponent and fraction widths.

Does frm rounding affect the VFWCVTBF16.F.F.V result?

No. BF16-to-FP32 widening is exact and does not round by frm. Vector FP instructions still require a valid frm, even at vl=0 or with no active elements.