Does VFSUB.VV use vxrm?
No. This instruction rounds using dynamic FP frm; vxrm controls fixed-point rounding. Only active-element FP exceptions accrue in fflags.
VFSUB.VV
RISC-V VFSUB.VV Instruction Details
Instruction ManualOPFVVVFSUB.VV computes vs2[i] - vs1[i] for active elements, rounding to SEW and writing vd[i].
Instruction Syntax
vfsub.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vfsub.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] - vs1[i] element by element. 32-bit OP-V: funct6=000010, funct3=001, opcode=1010111. Both inputs are SEW wide.
Vector source/result EEW=SEW and EMUL=LMUL; same-width destination/source overlap is legal. Equal sources require equal initial bits. Use VFRSUB.VF for scalar minus vector.
Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
VVector SubtractFloating-Point
Instruction Behavior
VFSUB.VV performs single-width FP subtraction. Vector inputs and results are SEW wide. Active elements compute vs2[i] - vs1[i]; subtract the second source from vs2. Results round using dynamic frm; only active-element exceptions accrue in fflags. Fixed-point vxrm is not used. V 1.0 provides FP32/FP64 on RV32/RV64 and depends on F/D; SEW=16 arithmetic requires Zvfh.
VFSUB.VV Decode And Execute Animation
Decode the OP-V encoding and execute lane-wise FP subtraction with the second source from same-lane vs1.
Instruction input
vfsub.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0x08861257
31..26
25
24..20
19..15
14..12
11..7
6..0
000010
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: 1 - 0.5 -> 0.5
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
1 - 0.5
0.5
i=1active
1.5 - 1
0.5
i=2skip
v0.t=0, not executed
--
i=3active
2.5 - 2
0.5
i=4active
-3 - 2.5
-5.5
i=5active
3.5 - 3
0.5
i=6skip
v0.t=0, not executed
--
i=7active
4.5 - 4
0.5
The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.
The teaching context fixes VLEN=4096, LMUL=m1, vstart=0, valid vtype, enabled VS/FS, FLEN=64, frm=RNE, and ta/ma. The selected binary32/64 subtraction is supported; same-width destination/source overlap is legal. Equal sources require equal initial bits. VF scalars at SEW=32 assume valid NaN-boxing. VL=0 updates no destination elements, including tails; other inactive/tail values are not specified in this display. Only finite RNE results are calculated, without NaNs, infinities, overflow, invalid NaN boxes, or full fflags; these model limits do not imply illegal architectural FP execution. Steps are not processor cycles.
Quick Understanding & Search Notes
VFSUB.VV is best understood through OP-V encoding, the same-lane vs1 element, v0.t masking, and per-element vd[i] = vs2[i] - vs1[i].
32-bit OP-V: funct6=000010, funct3=001, opcode=1010111.
The optional assembly operand v0.t means vm=0; omission means vm=1, unmasked.
Compute vs2[i] - vs1[i] element by element, not as a reduction.
Every vector FP instruction requires valid frm, even at vl=0; use of invalid frm is reserved.
Vector Execution Context
Syntax: vfsub.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] - vs1[i] element by element. 32-bit OP-V: funct6=000010, funct3=001, opcode=1010111. Both inputs are SEW wide.
Vector source/result EEW=SEW and EMUL=LMUL; same-width destination/source overlap is legal. Equal sources require equal initial bits. Use VFRSUB.VF for scalar minus vector.
Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
Common Usage Scenarios
Scientific Computing
Assume V/VS/FS enabled, valid vtype, supported FP formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Results are binary32; vector inputs are binary32. Omitting v0.t makes this unmasked: v2=[1,2,-3,0], v3=[0.5,0.5,0.5,0.5] → v1=[0.5,1.5,-3.5,-0.5]. Tails follow ta without guaranteed zeros.
Differences
Assume V/VS/FS enabled, valid vtype, supported FP formats, frm=RNE, e32,m1, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Results are binary32; vector inputs are binary32. Omitting v0.t makes this unmasked: v2=[1,2,-3,0], v3=[0.5,0.5,0.5,0.5] → v1=[0.5,1.5,-3.5,-0.5]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfsub.vv vd, vs2, vs1[, v0.t]. Compute vs2[i] - vs1[i] element by element. 32-bit OP-V: funct6=000010, funct3=001, opcode=1010111. Both inputs are SEW wide.
- Vector source/result EEW=SEW and EMUL=LMUL; same-width destination/source overlap is legal. Equal sources require equal initial bits. Use VFRSUB.VF for scalar minus vector.
Semantic Check
- Both vs2 and vs1 are vector sources; equal registers read equal initial bits. There is no FP scalar or immediate input.
- Optional v0.t means vm=0; omission means vm=1. Active elements satisfy vstart≤i<vl with the mask enabled. A masked destination cannot overlap v0; one source register cannot be read at both data EEW and mask EEW=1.
- Prestart elements do not update or raise exceptions. At vl=0 or vstart≥vl all destination elements, including tails, remain unchanged. Other inactive/tail values follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- Dynamic frm controls FP rounding; only active-element exceptions accrue in fflags. vxrm is not used. Valid frm is required even at vl=0; invalid frm use is reserved. V 1.0 supports FP32/FP64 on RV32/RV64 and depends on F/D. SEW=16 arithmetic requires Zvfh. Require valid vtype, supported widths, enabled VS/FS, and, with H and virtualization V=1, enabled vsstatus.VS/FS.
- The animation fixes LMUL=m1, VLEN=4096, vstart=0, FLEN=64, frm=RNE, and ta/ma. VF scalars at SEW=32 assume valid NaN-boxing. Only finite results are calculated, without NaNs, infinities, overflow, or full fflags; teaching steps are not processor cycles.
Pitfalls / Common Confusions
Operand order is vs2[i] - vs1[i]; use VFRSUB.VF for scalar minus vector.
Active elements satisfy vstart≤i<vl with the execution mask enabled. At vl=0 or vstart≥vl no destination elements change, including tails. ta/ma does not guarantee zeros.
V depends on F/D and supports FP32/FP64; SEW=16 arithmetic requires Zvfh and is not implied by V alone.
The animation computes finite RNE results only; NaNs, infinities, overflow, and full fflags are outside its model. The real instruction follows the official FP rules.
FAQ
Is vm an ordinary assembly immediate?
No. Optional v0.t denotes vm=0, while omission denotes vm=1. Do not write numeric 0 or 1 as an ordinary operand.