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VFSUB.VV

RISC-V VFSUB.VV Instruction Details

Instruction ManualR-type

VFSUB.VV performs vector-vector FP subtract on active elements within VL: vd[i] = vs2[i] - vs1[i].

Instruction Syntax

vfsub.vv vd, vs2, vs1, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VZvfhVector SubtractFloating-Point

Related Search Terms

VFSUB.VV instruction RISC-V VFSUB.VV vfsub.vv syntax vfsub.vv encoding RVV FP subtraction vfsub.vv mask execution vfsub.vv frm rounding

Instruction Behavior

VFSUB.VV is an RVV single-width floating-point subtraction instruction with syntax vfsub.vv vd, vs2, vs1, vm. Each active element uses the current SEW FP format to execute vd[i] = vs2[i] - vs1[i]; Operand order is vs2[i] - vs1[i]. With vm=0, v0.t controls active elements; with vm=1, execution is unmasked. Rounding mode and exception flags follow the official RVV floating-point rules, and fixed-point vxrm does not control these instructions.

VFSUB.VV Decode And Execute Animation

Decode the OP-V encoding and execute lane-wise FP subtraction with the second source from same-lane vs1.

Step 1 / 15

Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Instruction input

vfsub.vv

vdUse v0-v31vs2Use v0-v31vs1Use v0-v31vmexecution mask control

Execution context

VLSEW

frm

RNE

demo dynamic rounding mode

vta/vma

ta, ma

tail/inactive policy

opcode

1010111

OP-V major opcode

vs2 elementsComma-separated finite values, count must equal VL, representable as finite binary32vs1 elementsComma-separated finite values, count must equal VL, representable as finite binary32v0 mask bits0/1 string, length must equal VL

Encoding fields

0x08861257

31..26

24..20

19..15

14..12

11..7

6..0

000010

funct6

01000

vs2

01100

vs1

001

funct3

00100

1010111

OP-V

Lane results

Long vectors scroll inside this module without page overflow.

i=0active

1 - 0.5

0.5

i=1active

1.5 - 1

0.5

i=2skip

v0.t=0, not executed

i=3active

2.5 - 2

0.5

i=4active

-3 - 2.5

-5.5

i=5active

3.5 - 3

0.5

i=6skip

v0.t=0, not executed

i=7active

4.5 - 4

0.5

The animation quantizes source values and results for the current SEW under the RNE demo mode: SEW=32 uses binary32 and SEW=64 uses binary64. NaN, infinity, and exception flags still follow the official RVV FP rules and are not expanded here as a full FP exception simulator.

Quick Understanding & Search Notes

VFSUB.VV is best understood through OP-V encoding, the same-lane vs1 element, v0.t masking, and per-element vd[i] = vs2[i] - vs1[i].

funct6=000010, funct3=001, and opcode=1010111 identify this OP-V FP arithmetic form.

In vfsub.vv vd, vs2, vs1, vm, vm controls execution masking; vm=0 uses v0.t and vm=1 is unmasked.

For `.vv` forms, each lane reads vs2[i] and vs1[i]; this is not a reduction or cross-lane operation.

Results, NaNs, infinities, rounding, and fflags follow the official vector floating-point rules.

RISC-V Unprivileged ISA Manual: V extension vector floating-point instructions

Vector Execution Context

When reading VFSUB.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Scientific Computing

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfsub.vv v1, v2, v3 # v1[i] = v2[i] - v3[i]».

Differences

e.g., sub t0, a0, a1 — compute the difference a0 - a1.

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Operand order is vs2[i] - vs1[i].

Only elements within VL whose execution mask is true execute; inactive and tail elements follow the current vma/vta policy.

Ordinary RVV FP arithmetic uses the floating-point rounding environment frm / dynamic rounding semantics, not fixed-point vxrm.

Do not treat finite demo values in the browser animation as a full IEEE 754 exception simulator; NaN, infinity, and fflags follow the official manual.

FAQ

Does VFSUB.VV use vxrm?

No. Ordinary RVV FP arithmetic uses the floating-point rounding environment frm or the instruction-defined FP rounding rule; vxrm is for fixed-point rounding instructions.

What does the vm operand mean for VFSUB.VV?

vm=0 uses v0.t as the execution mask; vm=1 is unmasked. It is not an ordinary data source register.