Is vd output-only?
No. In the official definition, vd is the 2*SEW-wide addend and is overwritten by the final result; the animation exposes it as an editable accumulator input.
VFWMSAC.VF
RISC-V VFWMSAC.VF Instruction Details
Instruction ManualOPFVFwidening fused multiply-subtract-accumulator: f[rs1] and vs2[i] are SEW-wide multipliers, while wide vd[i] is the 2*SEW addend and result; (f[rs1] * vs2[i]) - vd[i].
Instruction Syntax
vfwmsac.vf vd, rs1, vs2, vm
Operand Breakdown
Syntax: vfwmsac.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111110. vd is both the wide input and wide result.
Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Old vd is also a wide source; narrow multipliers cannot share registers with its source group. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]) - old vd[i], with no separate product rounding and one fused rounding to the final double-width result. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
VVector Multiply-AddFloating-Point
Extension condition: V 1.0 on RV32/RV64, with supported FP formats and vtype and enabled VS/FS. Standard V supports the SEW=32-to-binary64 path shown here; this does not imply a supported binary128 result at SEW=64.
Instruction Behavior
VFWMSAC.VF overwrites the wide addend under the official RVV semantics: f[rs1] and vs2[i] are SEW-wide multipliers, while vd[i] is both the 2*SEW-wide input and result. Each active element evaluates (f[rs1] * vs2[i]) - vd[i] with one fused rounding to the wide result format. With vm=0, v0.t controls lane execution; this page's interactive example fixes a checkable SEW=32-to-binary64 path.
VFWMSAC.VF Decode And Execute Animation
Decode the OP-V encoding and execute widening fused multiply-add lane by lane: two SEW=32 multipliers and the 2*SEW=64 wide vd[i] produce one binary64 fused result; the second multiplier is scalar f[rs1].
Instruction input
vfwmsac.vf
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
acc/dest EEWvd is the FP64 wide addend and result
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xf8855257
31..26
25
24..20
19..15
14..12
11..7
6..0
111110
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(1, 1.5, -(0.5)) -> 1
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(1, 1.5, -(0.5))
1
i=1active
fma(1.5, 1.5, -(-1))
3.25
i=2skip
v0.t=0, not executed
--
i=3active
fma(2.5, 1.5, -(-2.5))
6.25
i=4active
fma(-3, 1.5, -(4))
-8.5
i=5active
fma(3.5, 1.5, -(-4.5))
9.75
i=6skip
v0.t=0, not executed
--
i=7active
fma(4.5, 1.5, -(-8.5))
15.25
This model fixes SEW=32, LMUL=m1, VLEN=4096, VLMAX=128, vstart=0, valid vtype, enabled VS/FS, and ta/ma. Multipliers are first represented as binary32, with binary64 results. Old vd is binary64; the fused operation rounds only the final result under RNE. Wide vd is also a source and cannot share registers with narrow multipliers. The scalar is read at FLEN=64 with valid NaN-boxing assumed. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model; the real instruction uses dynamic frm, with invalid frm use reserved even at VL=0.
Quick Understanding & Search Notes
Read f[rs1] and vs2[i] as SEW-wide multipliers, then fuse them with wide vd[i] as (f[rs1] * vs2[i]) - vd[i]; vd[i] is overwritten by the result.
The official widening FMA definition overwrites the wide addend: multiplier inputs are SEW, while the vd addend and destination elements are 2*SEW.
This instruction's per-element formula is vd[i] = (f[rs1] * vs2[i]) - vd[i].
The encoding is opcode=1010111 (OP-V), funct3=101 (OPFVF), funct6=111110.
Only active elements with vstart≤i<vl execute; with vm=0, v0.t decides whether a lane executes.
FP arithmetic uses frm; this interactive animation shows an exact fused calculation for finite binary32-to-binary64 inputs under RNE.
Narrow sources use EEW=SEW and EMUL=LMUL; the wide destination uses EEW=2*SEW and EMUL=2*LMUL. Encodings requiring EMUL>8 are reserved.
vd is also a wide source and cannot share registers with narrow multipliers; equal narrow sources read equal initial values.
Active elements satisfy vstart≤i<vl with the mask enabled; vl=0 or vstart≥vl updates no destination elements, including tails. ta/ma does not guarantee zeros; successful execution resets vstart=0.
The real instruction uses dynamic frm; invalid frm use is reserved even at vl=0. Only active-element FP exceptions accrue in fflags.
Vector Execution Context
Syntax: vfwmsac.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111110. vd is both the wide input and wide result.
Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Old vd is also a wide source; narrow multipliers cannot share registers with its source group. Equal narrow sources read equal initial values.
Each active element computes (f[rs1] * vs2[i]) - old vd[i], with no separate product rounding and one fused rounding to the final double-width result. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
Common Usage Scenarios
Fused binary32 products with a binary64 old destination
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. The FP scalar is validly NaN-boxed at FLEN=64. Omitting v0.t makes this unmasked: old v4/v5(binary64)=[1,2,-3,4], fa0=1.5, v8(binary32)=[2,4,-2,0] → v4/v5=[2,4,0,-4]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwmsac.vf vd, rs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=101, funct6=111110. vd is both the wide input and wide result.
- Narrow vector sources use EEW=SEW, EMUL=LMUL; vd uses EEW=2×SEW, EMUL=2×LMUL. Groups with EMUL=2/4/8 align to their size; EMUL>8 is reserved. Old vd is also a wide source; narrow multipliers cannot share registers with its source group. Equal narrow sources read equal initial values.
Semantic Check
- Each active element computes (f[rs1] * vs2[i]) - old vd[i], with no separate product rounding and one fused rounding to the final double-width result. The real instruction uses dynamic frm, not vxrm. rs1 selects an f register; when FLEN>SEW an invalid NaN box supplies canonical NaN. FLEN<SEW encodings are reserved.
- Omitting v0.t means vm=1; including it means vm=0. Only elements with vstart≤i<vl and an enabled mask execute and accrue FP exceptions to fflags. A masked destination cannot include v0; one register cannot be read as both an EEW=1 mask and different-EEW data source.
- Prestart elements do not update or raise exceptions; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported FP formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0. This animation fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, RNE, ta/ma, and finite inputs; it does not fully simulate NaNs, infinities, or fflags.
Pitfalls / Common Confusions
The official formula is vd[i] = (f[rs1] * vs2[i]) - vd[i]; vd is the wide addend overwritten by the result.
The two multipliers are SEW wide and vd is 2*SEW wide; do not treat this as scalar-width FMA or plain VFWMUL.
FMA rounds only at the final wide result; do not model it as a rounded product followed by addition.