Is vd output-only?
No. In the official definition, vd is the 2*SEW-wide addend and is overwritten by the final result; the animation exposes it as an editable accumulator input.
VFWNMSAC.VV
RISC-V VFWNMSAC.VV Instruction Details
Instruction ManualOPFVVwidening negate multiply-subtract-accumulator: vs1[i] and vs2[i] are SEW-wide multipliers, while wide vd[i] is the 2*SEW addend and result; -(vs1[i] * vs2[i]) + vd[i].
Instruction Syntax
vfwnmsac.vv vd, vs1, vs2[, v0.t]
Operand Breakdown
Syntax: vfwnmsac.vv vd, vs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=111111.
Narrow vector multipliers use EEW=SEW, EMUL=LMUL. vd is both the wide source and result, with EEW=2×SEW, EMUL=2×LMUL. EMUL=2/4/8 groups align to their size; EMUL>8 is reserved. Narrow multipliers cannot share registers with the wide vd source group; equal narrow sources read equal initial values.
Active elements compute -(vs1[i] * vs2[i]) + old vd[i], with no separate product rounding and one fused rounding to the final wide result. Both multipliers are same-index vector elements.
Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. A masked destination cannot include v0. Prestart elements do not update; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
VVector Multiply-AddFloating-Point
Extension condition: V 1.0 on RV32/RV64, with supported FP formats, valid vtype, and enabled VS/FS. Standard V supports SEW=32 to FP64, not a guaranteed SEW=64-to-FP128 path.
Instruction Behavior
VFWNMSAC.VV reads SEW-wide multipliers and 2*SEW-wide old vd, then evaluates -(vs1[i] * vs2[i]) + old vd[i] with one fused rounding to the wide result. Only active elements execute; the animation models finite FP32-to-FP64 inputs under RNE.
VFWNMSAC.VV Decode And Execute Animation
Decode the OP-V encoding and execute widening fused multiply-add lane by lane: two SEW=32 multipliers and the 2*SEW=64 wide vd[i] produce one binary64 fused result; the second multiplier is same-lane vs1.
Instruction input
vfwnmsac.vv
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
acc/dest EEWvd is the FP64 wide addend and result
vta/vmatail/inactive policy
opcodeOP-V major opcode
Encoding fields
0xfc861257
31..26
25
24..20
19..15
14..12
11..7
6..0
111111
funct6
0
vm
01000
vs2
01100
vs1
001
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: fma(-(1), 0.5, 0.5) -> 0
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
fma(-(1), 0.5, 0.5)
0
i=1active
fma(-(1.5), 1, -1)
-2.5
i=2skip
v0.t=0, not executed
--
i=3active
fma(-(2.5), 2, -2.5)
-7.5
i=4active
fma(-(-3), 2.5, 4)
11.5
i=5active
fma(-(3.5), 3, -4.5)
-15
i=6skip
v0.t=0, not executed
--
i=7active
fma(-(4.5), 4, -8.5)
-26.5
This model fixes SEW=32, LMUL=m1, VLEN=4096, VLMAX=128, vstart=0, valid vtype, enabled VS/FS, and ta/ma. Multipliers are first represented as binary32, with binary64 results. Old vd is binary64; the fused operation rounds only the final result under RNE. Wide vd is also a source and cannot share registers with narrow multipliers. Equal narrow source registers require equal initial bits. Inactive/tail elements have no definite displayed values; VL=0 updates no destination elements. NaNs, infinities, fflags, and microarchitectural cycles are outside this model; the real instruction uses dynamic frm, with invalid frm use reserved even at VL=0.
Quick Understanding & Search Notes
Read vs1[i] and vs2[i] as SEW-wide multipliers, then fuse them with wide vd[i] as -(vs1[i] * vs2[i]) + vd[i]; vd[i] is overwritten by the result.
Each active element computes -(vs1[i] * vs2[i]) + old vd[i]. Multipliers are SEW wide; old vd and the result are 2*SEW wide, with one fused rounding at the final wide result.
32-bit OP-V: opcode=1010111, funct3=001, funct6=111111. Both multipliers are same-index vector elements.
Narrow vector sources use EMUL=LMUL; wide vd uses EMUL=2*LMUL (at most 8, aligned to group size). Wide vd is also a source and cannot share registers with narrow multipliers. Equal narrow sources read equal initial values.
Active elements satisfy vstart≤i<vl with the mask enabled. vl=0 or vstart≥vl updates no destination elements; ta/ma does not guarantee zeros. Successful execution resets vstart=0.
The real instruction uses dynamic frm; invalid frm use is reserved even at vl=0. Active FP exceptions accrue in fflags; vxrm is not used.
Vector Execution Context
Syntax: vfwnmsac.vv vd, vs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=111111.
Narrow vector multipliers use EEW=SEW, EMUL=LMUL. vd is both the wide source and result, with EEW=2×SEW, EMUL=2×LMUL. EMUL=2/4/8 groups align to their size; EMUL>8 is reserved. Narrow multipliers cannot share registers with the wide vd source group; equal narrow sources read equal initial values.
Active elements compute -(vs1[i] * vs2[i]) + old vd[i], with no separate product rounding and one fused rounding to the final wide result. Both multipliers are same-index vector elements.
Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. A masked destination cannot include v0. Prestart elements do not update; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
Common Usage Scenarios
Widening Negated FMA
Assume enabled V/VS/FS, valid e32,m1, supported formats, frm=RNE, VLMAX≥4, and a0=4; vsetvli sets vl=4 and vstart=0. Omit v0.t for unmasked execution. old v4/v5(binary64)=[1,2,-3,4], v8(binary32)=[3,-1,2,5], v12(binary32)=[2,4,-2,0] → v4/v5=[-5,6,1,4]. Tails follow ta without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- Syntax: vfwnmsac.vv vd, vs1, vs2[, v0.t]. 32-bit OP-V: opcode=1010111, funct3=001, funct6=111111.
- Narrow vector multipliers use EEW=SEW, EMUL=LMUL. vd is both the wide source and result, with EEW=2×SEW, EMUL=2×LMUL. EMUL=2/4/8 groups align to their size; EMUL>8 is reserved. Narrow multipliers cannot share registers with the wide vd source group; equal narrow sources read equal initial values.
Semantic Check
- Active elements compute -(vs1[i] * vs2[i]) + old vd[i], with no separate product rounding and one fused rounding to the final wide result. Both multipliers are same-index vector elements.
- Omit v0.t for vm=1; include it for vm=0. Masked-off sources raise no FP exceptions; active exceptions accrue in fflags. One register cannot be read as both an EEW=1 mask and different-EEW data source. A masked destination cannot include v0. Prestart elements do not update; vl=0 or vstart≥vl updates no destination elements, including tails. Other inactive/tail elements follow vma/vta. ta/ma does not guarantee zeros; successful execution resets vstart=0.
- V 1.0 supports RV32/RV64 and depends on F/D. Require supported formats, valid vtype, and enabled VS/FS; with H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even at vl=0; vxrm is not used. This finite model fixes SEW=32, LMUL=m1, VLEN=4096, vstart=0, and RNE; NaNs, infinities, and fflags are not fully simulated.
Pitfalls / Common Confusions
The official formula is vd[i] = -(vs1[i] * vs2[i]) + vd[i]; vd is the wide addend overwritten by the result.
The two multipliers are SEW wide and vd is 2*SEW wide; do not treat this as scalar-width FMA or plain VFWMUL.
FMA rounds only at the final wide result; do not model it as a rounded product followed by addition.