How does VLE16FF.V differ from VLE16.V?
The address calculation and EEW are the same; VLE16FF.V differs by its fault-only-first exception rule, where a later active-element fault reduces vl to its index.
VLE16FF.V
RISC-V VLE16FF.V Instruction Details
Instruction ManualV-typeLoad 16-bit vector elements from x[rs1] with 2-byte unit stride; a synchronous fault after element 0 reduces vl to the faulting element index.
Instruction Syntax
vle16ff.v vd, (rs1), vm
Operand Breakdown
vd receives EEW=16-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×2 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
VVector MemoryFault-Only-First Load
Instruction Behavior
VLE16FF.V is the RISC-V V extension 16-bit unit-stride fault-only-first vector load. Active body elements read memory at x[rs1] + i * 2 bytes and write vd. A synchronous fault on element 0 is reported precisely like a normal load and does not modify vl; a synchronous fault after element 0 reduces vl to the index of the faulting element. With vm=0, v0.t selects accessed elements and masked-off elements do not access memory.
VLE16FF.V Decode And Execute Animation
Decode the 16-bit fault-only-first load, then compute each element address as x[rs1] + i * 2.
Instruction input
vle16ff.v
Execution context: EEW=16, unit stride=2 bytes, example SEW=16, LMUL=m1, vstart=0 (a nonzero value starts at that element), this example finishes with vl=5. These are not assembly syntax operands.
Teaching context: VLEN=4096, SEW=EEW=16, LMUL=EMUL=m1, VLMAX=256, vstart=0, valid vtype, enabled VS, and ta/ma. Base options are naturally aligned; rs1=x0 fixes the base at 0. Only the selected synchronous-fault scenario is modeled, assuming other selected memory is readable; actual system accessibility is not guaranteed. Per-element steps explain addresses and results, not access order or processor cycles. Inactive/tail elements may retain old values or become all ones; no definite result is shown. Normal completion resets vstart=0.
Encoding fieldsvle16ff.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
0
24..20
lumop
10000
19..15
rs1
01010
14..12
width
101
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 2 / vl'=5
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8002
0x8004
0x8006
0x8008
0x800a
0x800c
0x800e
0x8010
0x8012
0x8014
0x8016
0x8018
0x801a
0x801c
0x801e
mem
0x0011
0x0022
0x0033
0x0044
0x0055
0x0066
0x0077
0x0088
0x0099
0x00aa
0x00bb
0x00cc
0x00dd
0x00ee
0x00ff
0x0110
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLE16FF.V is still a unit-stride load: active element i uses x[rs1] + i * 2 bytes. Its special feature is the fault-only-first exception boundary: an element-0 fault traps normally, while a later active-element fault reduces vl to the faulting element index.
The encoding uses LOAD-FP, mop=00 for unit stride, width/mew for EEW=16, and lumop=10000 for the fault-only-first variant.
Address formation matches ordinary VLE16.V: participating body element i accesses x[rs1] + i * 2 bytes.
A synchronous exception on element 0 is reported precisely like a normal load; fault-only-first does not hide an element-0 fault by changing vl.
A synchronous exception after element 0 does not take that trap and reduces vl to the faulting element index; unfinished or newly out-of-range destination elements must not be taught as reliable loaded values.
With vm=0, body elements whose v0.t bit is 0 do not access memory. Inactive/tail elements normally follow vma/vta, but active destinations after an FF trimming point and within the original vl may receive values unrelated to memory; do not rely on them.
Data EEW=16 and EMUL=(EEW/SEW)×LMUL. EMUL must lie in 1/8 through 8, with a legal starting vd for that group. A masked load destination group must not overlap v0.
A misaligned element may transfer successfully or raise an address-misaligned exception; scalar misalignment support does not imply vector support. Unit-stride element accesses have no guaranteed order.
Body elements satisfy vstart≤i<vl; prestart elements stay undisturbed. VL=0 or vstart≥vl updates no destination elements, including tails. Normal completion resets vstart=0; V must be enabled and vtype valid.
On an interrupt, implementations should retain vl and set vstart. A debug data-watchpoint after the first element should trigger the debug trap without trimming vl. Non-idempotent memory may be accessed only when the corresponding load is known not to restart due to a trap or vl trimming.
Vector Execution Context
vd receives EEW=16-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×2 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
Common Usage Scenarios
Data-Dependent Exit Loops
Assume enabled V/VS, valid e16,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=2 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Contiguous Element Scanning
Assume enabled V/VS, valid e16,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=2 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Vector Loads That Can Trim vl
Assume enabled V/VS, valid e16,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=2 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- vd receives EEW=16-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
- rs1 is an integer base register; element i uses x[rs1]+i×2 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Semantic Check
- Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
- A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
- Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
Pitfalls / Common Confusions
The mnemonic fixes EEW=16, and unit-stride addresses advance by 2 bytes; this is not indexed gather or strided vlse.
Fault-only-first changes the exception boundary only: a synchronous fault on element 0 is still reported precisely like a normal load, and the instruction does not modify vl.
A synchronous fault after element 0 reduces vl to the faulting element index; do not infer that every later address was definitely accessed or definitely skipped.
Even without an exception, an implementation may process fewer than the original vl elements and reduce vl; with vstart=0 and vl>0, it must process at least one element.
With vm=0, elements disabled by v0.t do not perform memory accesses and cannot become the fault-only-first fault boundary.
FAQ
Does an element-0 fault in VLE16FF.V trim vl?
No. A synchronous exception on element 0 is a precise normal load trap; the instruction does not continue by modifying vl.
Can a v0.t-disabled element trigger VLE16FF.V fault-only-first behavior?
No. A masked-off body element performs no memory access, so it cannot become the fault boundary for this instruction.