Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VLE16FF.V
RISC-V VLE16FF.V Instruction Details
Instruction ManualV-typeLoad 16-bit vector elements from x[rs1] with 2-byte unit stride; a synchronous fault after element 0 can be represented by trimming vl.
Instruction Syntax
vle16ff.v vd, (rs1), vm
Operand Breakdown
vd: destination vector register group receiving loaded active elements.
rs1: integer base-address register; unit-stride forms read elements from consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryFault-Only-First Load
Instruction Behavior
VLE16FF.V is the RISC-V V extension 16-bit unit-stride fault-only-first vector load. Active body elements read memory at x[rs1] + i * 2 bytes and write vd. A synchronous fault on element 0 is reported precisely like a normal load and does not modify vl; a synchronous fault after element 0 may set vl to the index of the faulting element. With vm=0, v0.t selects accessed elements and masked-off elements do not access memory.
VLE16FF.V Decode And Execute Animation
Decode the 16-bit fault-only-first load, then compute each element address as x[rs1] + i * 2.
Instruction input
vle16ff.v
Execution context: EEW=16, unit stride=2 bytes, example SEW=16, LMUL=m1, resulting vl=5. These are not assembly syntax operands.
Encoding fieldsvle16ff.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
0
24..20
lumop
10000
19..15
rs1
01010
14..12
width
101
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 2 / vl'=5
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8002
0x8004
0x8006
0x8008
0x800a
0x800c
0x800e
0x8010
0x8012
0x8014
0x8016
0x8018
0x801a
0x801c
0x801e
mem
0x0011
0x0022
0x0033
0x0044
0x0055
0x0066
0x0077
0x0088
0x0099
0x00aa
0x00bb
0x00cc
0x00dd
0x00ee
0x00ff
0x0110
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLE16FF.V is still a unit-stride load: active element i uses x[rs1] + i * 2 bytes. Its special feature is the fault-only-first exception boundary: an element-0 fault traps normally, while a later active-element fault may trim vl to the faulting element index.
The encoding uses LOAD-FP, mop=00 for unit stride, width/mew for EEW=16, and lumop=10000 for the fault-only-first variant.
Address formation matches ordinary VLE16.V: participating body element i accesses x[rs1] + i * 2 bytes.
A synchronous exception on element 0 is reported precisely like a normal load; fault-only-first does not hide an element-0 fault by changing vl.
A synchronous exception after element 0 may stop the load and set vl to the faulting element index; unfinished or newly out-of-range destination elements must not be taught as reliable loaded values.
With vm=0, body elements whose v0.t bit is 0 do not perform memory accesses; tail and inactive destination elements follow the current vtype policies.
Vector Execution Context
When reading VLE16FF.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vectorized String Scan
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vle16ff.v v8, (a0), v0.t».
Contiguous Memory Probing
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vle16ff.v v8, (a0), v0.t».
Vector Loads That Can Trim vl
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vle16ff.v v8, (a0), v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The mnemonic fixes EEW=16, and unit-stride addresses advance by 2 bytes; this is not indexed gather or strided vlse.
Fault-only-first changes the exception boundary only: a synchronous fault on element 0 is still reported precisely like a normal load, and the instruction does not modify vl.
A synchronous fault after element 0 may be represented by trimming vl to the faulting element index; do not infer that every later address was definitely accessed or definitely skipped.
With vm=0, elements disabled by v0.t do not perform memory accesses and cannot become the fault-only-first fault boundary.
FAQ
How does VLE16FF.V differ from VLE16.V?
The address calculation and EEW are the same; VLE16FF.V differs by its fault-only-first exception rule, where a later active-element fault may be represented by trimming vl.
Does an element-0 fault in VLE16FF.V trim vl?
No. A synchronous exception on element 0 is a precise normal load trap; the instruction does not continue by modifying vl.
Can a v0.t-disabled element trigger VLE16FF.V fault-only-first behavior?
No. A masked-off body element performs no memory access, so it cannot become the fault boundary for this instruction.