What unit is used for VLE16FF.V address offsets?
Unit-stride loads advance by the instruction EEW for consecutive elements.
VLE16FF.V
RISC-V VLE16FF.V Instruction Details
Instruction ManualR-typePerform a 16-bit unit-stride fault-only-first load from x[rs1]; a fault after element 0 can reduce vl.
Instruction Syntax
vle16ff.v vd, (rs1), vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector LoadMemory Access
Instruction Behavior
VLE16FF.V is a RISC-V V 16-bit fault-only-first vector load instruction. It is the fault-only-first form of a unit-stride load; if a synchronous exception occurs after element 0, the implementation may reduce vl to the number of elements loaded successfully; an element-0 fault is reported precisely like an ordinary load. It operates on active elements within vl, with masking and tail behavior following RVV rules.
Quick Understanding & Search Notes
FF loads treat element-0 faults as the normal trap boundary; faults after element 0 can be represented by reducing vl.
EEW=16; destination elements are interpreted under the current SEW/LMUL configuration and instruction EEW rules.
Only an element-0 fault must be reported precisely; a later fault may terminate the load by updating vl.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
Memory Load
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vle16ff.v v1, (a0)».
Array Traversal
Understand this scenario with real code like «vsetvli t0, a0, e16, m1, ta, ma vle16ff.v v1, (a0)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The instruction EEW=16 fixes the memory element width; the current vtype must make the derived EEW/SEW EMUL legal.
vm=0 uses v0 to mask elements and vm=1 is unmasked; masked-off elements do not perform memory accesses.
Fault-only-first treats an element-0 fault as the normal trap boundary; a synchronous fault after element 0 can be represented by reducing vl.
FAQ
How does VLE16FF.V handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.