How does VLE8FF.V differ from VLE8.V?
The address calculation and EEW are the same; VLE8FF.V differs by its fault-only-first exception rule, where a later active-element synchronous fault reduces vl to the faulting element index.
VLE8FF.V
RISC-V VLE8FF.V Instruction Details
Instruction ManualV-typeLoad 8-bit vector elements from x[rs1] with 1-byte unit stride; a synchronous fault after element 0 reduces vl to the faulting element index.
Instruction Syntax
vle8ff.v vd, (rs1), vm
Operand Breakdown
vd receives EEW=8-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×1 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
VVector MemoryFault-Only-First Load
Instruction Behavior
VLE8FF.V is the RISC-V V extension 8-bit unit-stride fault-only-first vector load. Active body elements read memory at x[rs1] + i * 1 byte and write vd. A synchronous fault on element 0 is reported precisely like a normal load and does not modify vl; a synchronous fault after element 0 does not take that trap and reduces vl to the index of the faulting element. With vm=0, v0.t selects accessed elements and masked-off elements do not access memory.
VLE8FF.V Decode And Execute Animation
Decode the 8-bit fault-only-first load, then compute each element address as x[rs1] + i * 1.
Instruction input
vle8ff.v
Execution context: EEW=8, unit stride=1 bytes, example SEW=8, LMUL=m1, vstart=0 (a nonzero value starts at that element), this example finishes with vl=5. These are not assembly syntax operands.
Teaching context: VLEN=4096, SEW=EEW=8, LMUL=EMUL=m1, VLMAX=512, vstart=0, valid vtype, enabled VS, and ta/ma. Base options are naturally aligned; rs1=x0 fixes the base at 0. Only the selected synchronous-fault scenario is modeled, assuming other selected memory is readable; actual system accessibility is not guaranteed. Per-element steps explain addresses and results, not access order or processor cycles. Inactive/tail elements may retain old values or become all ones; no definite result is shown. Normal completion resets vstart=0.
Encoding fieldsvle8ff.v / LOAD-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
0
24..20
lumop
10000
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
01000
6..0
opcode
0000111
Address and data pathaddr[i] = 0x8000 + i * 1 / vl'=5
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
addr
0x8000
0x8001
0x8002
0x8003
0x8004
0x8005
0x8006
0x8007
0x8008
0x8009
0x800a
0x800b
0x800c
0x800d
0x800e
0x800f
mem
0x03
0x06
0x09
0x0c
0x0f
0x12
0x15
0x18
0x1b
0x1e
0x21
0x24
0x27
0x2a
0x2d
0x30
active
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
v8
...
...
-
...
...
...
...
-
...
...
...
...
-
...
...
...
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
VLE8FF.V is still a unit-stride load: active element i uses x[rs1] + i * 1 byte. Its special feature is the fault-only-first exception boundary: an element-0 fault traps normally, while a later active-element synchronous fault reduces vl to the faulting element index.
The encoding uses LOAD-FP, mop=00 for unit stride, width/mew for EEW=8, and lumop=10000 for the fault-only-first variant.
Address formation matches ordinary VLE8.V: participating body element i accesses x[rs1] + i * 1 byte.
A synchronous exception on element 0 is reported precisely like a normal load; fault-only-first does not hide an element-0 fault by changing vl.
A synchronous exception after element 0 does not take that trap and reduces vl to the faulting element index; unfinished or newly out-of-range destination elements must not be taught as reliable loaded values.
With vm=0, body elements whose v0.t bit is 0 do not perform memory accesses; tail and inactive destination elements follow the current vtype policies.
EEW=8 does not require SEW=8: data EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal group start; unsupported EEW encodings are reserved. Require enabled V/VS and valid vtype.
Body elements satisfy vstart≤i<vl; masked vd must not overlap v0. Prestart stays unchanged; vl=0 or vstart≥vl updates no destination, including tails. Unit stride guarantees no element access order; misalignment may succeed or raise an address-misaligned exception.
Element 0 means index 0, not the first active element. Even without a fault, fewer elements may be processed and vl reduced; vstart=0 and original vl>0 require processing at least one element. On interrupts implementations should keep vl and set vstart; a later debug watchpoint should take the debug trap instead of trimming vl.
32-bit LOAD-FP: opcode=0000111, nf=000, mew=0, mop=00, width=000, lumop=10000. In syntax, vm means optional v0.t or omission, not a register named vm.
Vector Execution Context
vd receives EEW=8-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
rs1 is an integer base register; element i uses x[rs1]+i×1 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
Common Usage Scenarios
Vectorized String Scan
Assume enabled V/VS, valid e8,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=1 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Contiguous Memory Probing
Assume enabled V/VS, valid e8,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=1 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Vector Loads That Can Trim vl
Assume enabled V/VS, valid e8,m1, VLMAX≥4, AVL=4, and vl=4, vstart=0, ta/ma after vsetvli; destination does not overlap source masks. Memory is readable except for the selected fault; address step=1 bytes: a0=0x8000, v0=[1,0,1,1], mem=[10,20,30,40] → vd=[10,agnostic,30,unreliable], element 3 synchronous fault → vl=3, no fault trap. Agnostic elements may retain old values or become all ones, without guaranteed zeros.
Pre-Use Checklist
Syntax Check
- vd receives EEW=8-bit memory bit patterns; EMUL=(EEW/SEW)×LMUL must be in 1/8..8 with a legal register-group start. Elements are not extended into XLEN-wide scalars.
- rs1 is an integer base register; element i uses x[rs1]+i×1 bytes, with base 0 for rs1=x0. v0.t gives vm=0; omitting it gives vm=1.
Semantic Check
- Require enabled V and valid vtype. Active body elements satisfy vstart≤i<vl and mask enabled; masked vd cannot cover v0. Disabled elements access no memory; inactive/tail follow vma/vta and prestart stays unchanged. VL=0 or vstart≥vl updates no destination.
- A synchronous fault on element 0 traps with vl unchanged; one on element i>0 suppresses that trap and sets vl=i. This is the element index, not the first active element. vl may shrink even without a fault; vstart=0 and original vl>0 require processing at least one element.
- Active destinations beyond FF trimming but within original vl may receive values unrelated to memory. On an interrupt implementations should keep vl and set vstart; a later debug watchpoint should trigger the debug trap instead of trimming vl.
Pitfalls / Common Confusions
The mnemonic fixes EEW=8, and unit-stride addresses advance by 1 byte; this is not indexed gather or strided vlse.
A key fault-only-first difference is the synchronous-exception boundary: a synchronous fault on element 0 is still reported precisely like a normal load, and the instruction does not modify vl.
A synchronous fault after element 0 does not take that trap and reduces vl to the faulting element index; do not infer that every later address was definitely accessed or definitely skipped.
With vm=0, elements disabled by v0.t do not perform memory accesses and cannot become the fault-only-first fault boundary.
FAQ
Does an element-0 fault in VLE8FF.V trim vl?
No. A synchronous exception on element 0 is a precise normal load trap; the instruction does not continue by modifying vl.
Can a v0.t-disabled element trigger VLE8FF.V fault-only-first behavior?
No. A masked-off body element performs no memory access, so it cannot become the fault boundary for this instruction.