Does VMSLE.VV write ordinary vector elements?
No. Compare instructions write a mask destination vd, with one Boolean bit per element.
VMSLE.VV
RISC-V VMSLE.VV Instruction Details
Instruction ManualR-typePerform element-wise <= comparison and write the Boolean result to mask destination vd.
Instruction Syntax
vmsle.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector IntegerCompare
Instruction Behavior
VMSLE.VV is a RISC-V V vector integer signed less-or-equal compare instruction. For active elements within vl, it compares vs2 with vs1 and writes the comparison result to mask destination vd. Source operands are interpreted at the current SEW according to this instruction's comparison relation. Integer comparisons do not raise floating-point exceptions.
Quick Understanding & Search Notes
VMSLE.VV produces mask bits, not a 0/-1 integer vector.
The destination stores Boolean results in mask-register layout, one bit per element.
Signed comparison determines the result; source operands are interpreted at SEW.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
Conditional Execution
Understand this scenario with real code like «vmsle.vv v1, v2, v4».
Range Check
Understand this scenario with real code like «vmsle.vv v1, v2, v4».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Integer compares raise no FP exceptions
Result always tail-agnostic
FAQ
How does VMSLE.VV handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.