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VNSRA.WX

RISC-V VNSRA.WX Instruction Details

Instruction ManualR-type

arithmetic narrowing right shift from 2*SEW source elements to SEW results.

Instruction Syntax

vnsra.wx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerShift/Narrowing
Related Search Terms
VNSRA.WX instructionvnsra.wx syntaxvnsra.wx narrowing shiftRVV narrowing shiftarithmetic shift

Instruction Behavior

VNSRA.WX performs a arithmetic right shift on 2*SEW-wide source elements and writes SEW-width destination elements. The shift amount comes from a scalar integer register.

Quick Understanding & Search Notes

VNSRA.WX shrinks wide integer results back to SEW width using a arithmetic right shift.

Source elements are 2*SEW wide and destination elements are SEW wide.
Arithmetic right shift preserves sign-extension semantics.
This instruction does not use vxrm rounding and does not set the vxsat saturation flag.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VNSRA.WX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Fixed-Point Scaling

Understand this scenario with real code like «vnsra.wx v8, v12, x5, v0.t».

Precision Reduction

Understand this scenario with real code like «vnsra.wx v8, v12, x5, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Shift 0+rs1=x0=narrowing type conversion (pseudo vncvt.x.x.w)

FAQ

Does VNSRA.WX round?

No. It is a narrowing right shift; use VNCLIP/VNCLIPU when fixed-point rounding and saturation are required.