Does VNSRA.WX round?
No. It is a narrowing right shift; use VNCLIP/VNCLIPU when fixed-point rounding and saturation are required.
VNSRA.WX
RISC-V VNSRA.WX Instruction Details
Instruction ManualOPIVXArithmetic narrowing right shift from 2*SEW source elements to SEW results.
Instruction Syntax
vnsra.wx vd, vs2, rs1, vm
Operand Breakdown
Syntax: vnsra.wx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101101, funct3=100.
vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Arithmetic-right-shift the signed wide source, then take low SEW bits, without vxrm rounding or vxsat updates. vd may overlap the wide source only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot share registers with the wide source.
rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
Only low lg2(2*SEW) count bits are used; .wi can encode only 0–31 even when 2*SEW permits larger counts. Group starts align to EMUL, with EMUL≤8; the implementation must support both widths.
Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
VVector IntegerShift/Narrowing
Instruction Behavior
VNSRA.WX performs an arithmetic right shift on signed 2*SEW-wide source elements and writes the low SEW bits to destination elements. The shift amount comes from a scalar integer register.
VNSRA.WX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VNSRA reads signed 2*SEW-wide vs2, takes the low lg2(2*SEW) shift-count bits for an arithmetic right shift, and writes the low SEW bits to vd.
Instruction input
vnsra.wx
Require enabled vector state, valid vtype, and support for source 2*SEW and destination SEW; VL=0 updates no destination elements. Same-start narrow-destination/wide-source overlap is legal and forces mask- and tail-agnostic behavior. Only body elements are shown; no definite inactive or tail values are invented.
Execution Context
Shift-count rule: only the low lg2(2*SEW) bits of the x[rs1] value are used.
The teaching model fixes LMUL=m1, vstart=0, and VLEN=4096, so VLMAX=4096/16=256. Only body elements for selected VL=8 are shown; support for source 2*SEW and destination SEW is assumed. Wide vs2 has EMUL=2 and must start at an even register; .wv vs1 cannot overlap the wide source group. No definite inactive or tail results are shown; legal different-EEW overlap forces agnostic behavior. Steps are teaching stages, not processor cycles.
OP-V encodingvnsra.wx
funct6
101101
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00001234
0x80000040
0x000000ff
0xffffffe0
0x00010000
0x00000007
0x00001234
0x80000040
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
narrow>>
x11
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vnsra.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW-to-SEW integer arithmetic narrowing right shift, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VNSRA.WX shrinks wide integer results back to SEW width with an arithmetic right shift.
Source elements are 2*SEW wide and destination elements are SEW wide.
Arithmetic right shift preserves sign-extension semantics.
This instruction does not use vxrm rounding and does not set the vxsat saturation flag.
Requires V, enabled vector state, valid vtype, and supported element widths; VL=0 updates no destination elements, including tails.
With vm=0, only body elements with v0.mask[i]=1 execute; inactive/tail elements follow vma/vta and are not guaranteed to be preserved.
rs1 is an integer x register: use its low SEW bits when XLEN>SEW and sign-extend when XLEN<SEW; x0 supplies zero.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120) — 31.11.7. Vector Narrowing Integer Right Shift InstructionsThe RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version 20260120) — 31.5. Vector Instruction Formats; 31.10. Vector Arithmetic Instruction Formats; 31.20. Vector Instruction Listing
Vector Execution Context
Syntax: vnsra.wx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101101, funct3=100.
vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Arithmetic-right-shift the signed wide source, then take low SEW bits, without vxrm rounding or vxsat updates. vd may overlap the wide source only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot share registers with the wide source.
rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
Only low lg2(2*SEW) count bits are used; .wi can encode only 0–31 even when 2*SEW permits larger counts. Group starts align to EMUL, with EMUL≤8; the implementation must support both widths.
Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Common Usage Scenarios
Wide integer field extraction
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[-17,32767,-32768,-1], x5=4 → v8=[254,255,0,255]. Arithmetic-right-shift signed 16-bit sources by 4, then take low 8 bits, without rounding or saturation. Inactive/tail values follow policy without assumed zeroing.
2*SEW-to-SEW narrowing
Assume enabled V/VS, valid m1, VLEN≥128, supported operand widths, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v12=[-17,32767,-32768,-1], x5=4 → v8=[254,255,0,255]. Arithmetic-right-shift signed 16-bit sources by 4, then take low 8 bits, without rounding or saturation. Inactive/tail values follow policy without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vnsra.wx vd, vs2, rs1[, v0.t]; omit v0.t for vm=1 and include it for vm=0. 32-bit OP-V: opcode=1010111, funct6=101101, funct3=100.
- vd is the SEW/LMUL narrow destination; vs2 is the 2*SEW/2*LMUL wide source. Arithmetic-right-shift the signed wide source, then take low SEW bits, without vxrm rounding or vxsat updates. vd may overlap the wide source only at the same lowest register, forcing mask/tail agnostic; .wv vs1 cannot share registers with the wide source.
Semantic Check
- rs1 is an integer x register: XLEN>SEW takes low SEW bits, XLEN<SEW sign-extends; x0 supplies zero.
- Only low lg2(2*SEW) count bits are used; .wi can encode only 0–31 even when 2*SEW permits larger counts. Group starts align to EMUL, with EMUL≤8; the implementation must support both widths.
- Require V 1.0, enabled vector state, and valid supported vtype. Masked vd cannot contain v0; v0 cannot supply both the EEW=1 mask and data. Active body satisfies vstart≤i<vl with mask enabled; prestart is unchanged and inactive/tail follow vma/vta. vstart≥vl (including vl=0) updates no destination elements.
Pitfalls / Common Confusions
rs1 becomes a SEW-width count by the .vx scalar rule; only low lg2(2*SEW) bits are used, and x0 supplies count zero.
Masked vd cannot be v0; v0 cannot supply both the EEW=1 mask and a data source.
vs2 uses EEW=2*SEW and EMUL=2*LMUL; vd and .wv vs1 use SEW/LMUL. Source groups must be legal and EMUL≤8.
A narrow destination may overlap its wide source only at the same lowest register; different-EEW sources cannot share a register. Legal different-EEW source/destination overlap forces mask/tail agnostic behavior.