Where are the VREDMAXU.VS seed and result?
The seed is vs1[0]. With vl>0, only vd[0] in a single register receives the SEW result; the rest is tail governed by vta.
VREDMAXU.VS
RISC-V VREDMAXU.VS Instruction Details
Instruction ManualOPMVV (OP-V)VREDMAXU.VS: with vl>0, reduce active vs2 elements and seed vs1[0] by unsigned maximum, writing the result to vd[0].
Instruction Syntax
vredmaxu.vs vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vredmaxu.vs vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000110.
vs2 is a SEW/LMUL vector group; vs1[0] is a SEW seed and vd[0] is the SEW result. Each scalar occupies a single vector register regardless of LMUL.
With vl>0, always include vs1[0] and reduce only active vs2 elements; all-masked-off still writes the seed to vd[0]. The rest of vd is tail governed by vta: retain or agnostic. vl=0 leaves all of vd unchanged. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources and v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot supply both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
VVector Reduction
Instruction Behavior
VREDMAXU.VS is a V 1.0 single-width integer unsigned maximum reduction. With vl>0 and vstart=0, always include vs1[0] and reduce active vs2 elements by maxu; write the SEW result to vd[0] in one register. Other destination elements are tail; vl=0 leaves vd unchanged.
VREDMAXU.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VREDMAXU uses vs1[0] as the seed, reduces only active vs2 elements, and writes the SEW-width result to vd[0].
Instruction input
vredmaxu.vs
Require V 1.0, enabled vector state and valid supported vtype/SEW. Fix LMUL=m1, vstart=0, VLEN=4096 and VLMAX=4096/16=256. A nonzero vstart for a reduction raises an illegal-instruction exception, so it is not offered as an executable input. A reduction writes element 0 of one vd; the rest is tail governed by vta. vd may overlap sources or v0. With vs2=vs1, the seed must equal vs2[0]. When v0 supplies the EEW=1 mask it cannot also supply SEW data. VL=0 updates no destination elements. Only body is shown without definite inactive/tail values. Steps are teaching stages, not processor cycles.
Execution Context
OP-V encodingvredmaxu.vs
funct6
000110
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x0004
0x0004
0x0004
0x0011
0x0011
0x0011
0x0011
0x0011
v8
0x0004
0x0009
0x0011
0x0002
0x0007
0x0020
0x0004
0x0009
max
max
max
max
max
max
max
max
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vredmaxu.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, integer unsigned maximum reduction seeded by vs1[0], mask participation filtering, and vd[0] writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VREDMAXU.VS: with vl>0, reduce active vs2 elements and seed vs1[0] by unsigned maximum, writing the result to vd[0].
32-bit OP-V OPMVV: opcode=1010111, funct3=010, funct6=000110. vs2 is a vector group; vs1[0]/vd[0] are scalars in single registers.
All operands/results have SEW bits: unsigned maximum reduction. Always include vs1[0], irrespective of the mask; include only active vs2 elements. Compare unsigned integers.
With vl>0, write only vd[0]; other destination elements are tail governed by vta. If all vs2 elements are masked off, write the seed.
vl=0 performs no operation and leaves all of vd unchanged. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources and v0. Source groups align to LMUL; equal vs2/vs1 require seed=vs2[0]. v0 cannot supply both the EEW=1 mask and SEW source data. Require V 1.0, enabled vector state and valid supported vtype.
Vector Execution Context
Syntax: vredmaxu.vs vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000110.
vs2 is a SEW/LMUL vector group; vs1[0] is a SEW seed and vd[0] is the SEW result. Each scalar occupies a single vector register regardless of LMUL.
With vl>0, always include vs1[0] and reduce only active vs2 elements; all-masked-off still writes the seed to vd[0]. The rest of vd is tail governed by vta: retain or agnostic. vl=0 leaves all of vd unchanged. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources and v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot supply both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
Common Usage Scenarios
Reduce a vector and seed by unsigned maximum
Assume enabled V/VS, valid m1, VLEN≥128, supported SEW, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, v4[0]=4, v12=[1,128,2,3] → v8[0]=128. Include the seed, then reduce all active source elements; other destination elements are tail governed by vta. vl=0 leaves the destination unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vredmaxu.vs vd, vs2, vs1[, v0.t]; omit v0.t for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=010 (OPMVV), funct6=000110.
- vs2 is a SEW/LMUL vector group; vs1[0] is a SEW seed and vd[0] is the SEW result. Each scalar occupies a single vector register regardless of LMUL.
Semantic Check
- With vl>0, always include vs1[0] and reduce only active vs2 elements; all-masked-off still writes the seed to vd[0]. The rest of vd is tail governed by vta: retain or agnostic. vl=0 leaves all of vd unchanged. Nonzero vstart raises an illegal-instruction exception.
- vd may overlap sources and v0. Equal vs2/vs1 must read a consistent element 0 from the same register. v0 cannot supply both the EEW=1 mask and SEW data. Source-group starts align to EMUL, EMUL≤8.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. Successful execution resets vstart to 0. The animation uses its stated m1/vstart=0 assumptions; its steps are not processor cycles.
Pitfalls / Common Confusions
vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.
When vl=0, no reduction is performed and vd is not updated; a distinct vd does not receive a copy of the seed.
FAQ
Are all-masked-off and vl=0 equivalent for VREDMAXU.VS?
No. With vl>0 and every vs2 element masked off, write the seed to vd[0]. With vl=0, leave all of vd unchanged. Nonzero vstart raises an illegal-instruction exception.