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VREDMAXU.VS

RISC-V VREDMAXU.VS Instruction Details

Instruction ManualR-type

VREDMAXU.VS uses the vs1[0] seed to perform unsigned maximum reduction over active vs2 elements, writing only vd[0].

Instruction Syntax

vredmaxu.vs vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group, with the reduction result written to element 0.
vs2: vector source being reduced.
vs1[0]: reduction seed, not a second element-wise vector source.
VVector Reduction
Related Search Terms
vredmaxu.vs instructionRISC-V vredmaxu.vsvredmaxu.vs syntaxvredmaxu.vs encodingRVV unsigned maximum reductionvredmaxu.vs vd[0]

Instruction Behavior

VREDMAXU.VS is a RISC-V V extension unsigned integer reduction instruction. Syntax is `vredmaxu.vs vd, vs2, vs1, vm`; it uses vs1[0] as the seed, includes only masked-in active vs2 elements within the current vl in the unsigned maximum reduction, and writes the final SEW-width result to vd[0]. Comparisons interpret bit patterns as unsigned integers.

VREDMAXU.VS Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VREDMAXU uses vs1[0] as the seed, reduces only active vs2 elements, and writes the SEW-width result to vd[0].

Instruction input
vredmaxu.vs
OP-V encodingvredmaxu.vs
funct6
000110
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x0004
0x0004
0x0004
0x0011
0x0011
0x0011
0x0011
0x0011
v8
0x0004
0x0009
0x0011
0x0002
0x0007
0x0020
0x0004
0x0009
max
max
max
max
max
max
max
max
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step

Show OP-V 32-bit encoding fields

vredmaxu.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, vs1[0]-seeded reduction integer unsigned maximum reduction, mask participation filtering, and vd[0] writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VREDMAXU.VS is a single-width integer reduction instruction; the result is collected in element 0 of the destination vector register.

vs1[0] supplies the reduction seed; vs1 is not a second element-wise vector source.
Only active elements participate; masked-off elements do not contribute.
The reduction result is written to vd[0]; other destination elements follow tail policy.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VREDMAXU.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Global Aggregate

Understand this scenario with real code like «vredmaxu.vs v8, v12, v4, v0.t».

Normalization

Understand this scenario with real code like «vredmaxu.vs v8, v12, v4, v0.t».

Condition

Use jal x0, target or j target.

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.

FAQ

Does VREDMAXU.VS write the reduction result to every element?

No. The effective integer reduction result is written to vd[0], not broadcast element-wise.