Does VREDMIN.VS write the reduction result to every element?
No. The effective integer reduction result is written to vd[0], not broadcast element-wise.
VREDMIN.VS
RISC-V VREDMIN.VS Instruction Details
Instruction ManualR-typeReduce active elements and a scalar seed using signed minimum.
Instruction Syntax
vredmin.vs vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Reduction
Instruction Behavior
VREDMIN.VS uses vs1[0] as the scalar seed, reduces active elements of vs2 with signed minimum, and writes the result to vd[0].
Quick Understanding & Search Notes
VREDMIN.VS is a single-width integer reduction instruction; the result is collected in element 0 of the destination vector register.
vs1[0] supplies the reduction seed; vs1 is not a second element-wise vector source.
Only active elements participate; masked-off elements do not contribute.
The reduction result is written to vd[0]; other destination elements follow tail policy.
Common Usage Scenarios
Global Aggregate
Understand this scenario with real code like «vredmin.vs v8, v12, v4, v0.t».
Normalization
Understand this scenario with real code like «vredmin.vs v8, v12, v4, v0.t».
Condition
Use jal x0, target or j target.
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Scalar vs1[0] always participates regardless of mask
Result only in element 0
vstart must be 0