How does VROL.VV use masking?
The optional assembly operand is v0.t: omit it for vm=1 or include it for vm=0. The masked destination vd must not overlap v0.
VROL.VV
RISC-V VROL.VV Instruction Details
Instruction ManualOP-V OPIVV (funct6=010101, funct3=000)Vector rotate left by vector: rotate vs2[i] left by vs1[i] bits
Instruction Syntax
vrol.vv vd, vs2, vs1, vm
Syntax: vrol.vv vd, vs2, vs1[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
32-bit OP-V: funct6=010101, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Rotate each active vs2 element left by the low log2(SEW) bits of the corresponding vs1 element, keeping SEW-bit results.
Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
ZvbbZvkbVector Bit Manipulation
Instruction Behavior
vrol.vv is the Zvbb vector rotate-left instruction. Each element vs2[i] is rotated left by vs1[i] mod SEW bits. Rotate means shifted-out bits wrap around to the other end using the current legal SEW configuration.
VROL.VV Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..26
funct6
010101
25
vm
1
24..20
vs2
01000
19..15
vs1
01100
14..12
funct3
000
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct6=010101, funct3=000, Zvbb/Zvkb
v4[0] <- pending
Quick Understanding & Search Notes
Rotates each active vs2 element left using the low log2(SEW) bits of the corresponding vs1 element; the result remains SEW bits wide.
Each vs2 element is rotated left by the corresponding vs1 element amount modulo SEW.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Both Zvbb and Zvkb provide this instruction and depend on Zve32x: SEW=8/16/32; SEW=64 additionally requires Zve64x.
Body elements satisfy vstart≤i<vl; prestart is undisturbed and inactive/tail follow vma/vta. With vstart≥vl (including vl=0), all destination elements are undisturbed; success resets vstart=0.
vm=0 uses v0.t: vd must not be v0 and v0 cannot also be a SEW data source. Same-EEW data sources may overlap the destination. Nonzero vstart requires implementation support.
Vector Execution Context
Syntax: vrol.vv vd, vs2, vs1[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
32-bit OP-V: funct6=010101, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Rotate each active vs2 element left by the low log2(SEW) bits of the corresponding vs1 element, keeping SEW-bit results.
Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
Common Usage Scenarios
Crypto & Security
With the listed extension and vector state enabled, legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678, v12[0]=4: v4[0]=0x23456781. Only the active group/element is shown; tu keeps tails undisturbed. Success resets vstart=0.
Vector Acceleration
With the listed extension and vector state enabled, legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678, v12[0]=4: v4[0]=0x23456781. Only the active group/element is shown; tu keeps tails undisturbed. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vrol.vv vd, vs2, vs1[, v0.t]. Vector registers select v0–v31. Omit v0.t for vm=1 or include it for vm=0. No immediate operand.
- 32-bit OP-V: funct6=010101, vm[25], vs2[24:20], vs1[19:15], funct3=000, vd[11:7], opcode=1010111.
Semantic Check
- Zvbb or Zvkb depends on Zve32x and supports SEW=8/16/32, with 64 additionally requiring Zve64x. Rotate each active vs2 element left by the low log2(SEW) bits of the corresponding vs1 element, keeping SEW-bit results.
- Enable vector state with a legal supported vtype. Same-width sources/destination may overlap, reading original values; LMUL>1 groups must be aligned. With vm=0, vd must not overlap v0, which cannot supply both SEW data and an EEW=1 mask.
- Only active body elements are processed. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; successful execution resets vstart. Unsupported nonzero vstart may be rejected by the implementation.
Pitfalls / Common Confusions
Rotate left: shifted-out bits wrap around, not equivalent to plain shift.
Shift amount is modulo SEW.
FAQ
What determines the element width for VROL.VV?
A legal, supported vtype.SEW selects 8, 16 or 32 bits with Zve32x; 64 bits additionally requires Zve64x.