Can VROL.VV always use a v0.t mask?
It can use the vm mask operand shown in the syntax; omitting it gives the unmasked form.
VROL.VV
RISC-V VROL.VV Instruction Details
Instruction ManualR-typeVector rotate left by vector: rotate vs2[i] left by vs1[i] bits
Instruction Syntax
vrol.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbbVector Bit Manipulation
Instruction Behavior
vrol.vv is the Zvbb vector rotate-left instruction. Each element vs2[i] is rotated left by vs1[i] mod SEW bits. Rotate means shifted-out bits wrap around to the other end. Supports all SEW.
Quick Understanding & Search Notes
VROL.VV is a Zvbb vector instruction for vector rotate left. This page is checked against the official vector crypto extension and V-extension execution model.
Each vs2 element is rotated left by the corresponding vs1 element amount modulo SEW.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vrol.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vrol.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Rotate left: shifted-out bits wrap around, not equivalent to plain shift.
Shift amount is modulo SEW.
FAQ
What determines the element width for VROL.VV?
The current vtype SEW determines it, subject to any instruction-specific SEW restrictions in the extension.