Does VROR.VV change element width?
No. The result element width remains the current SEW.
VROR.VV
RISC-V VROR.VV Instruction Details
Instruction ManualR-typeVector rotate right by vector amount; each vs2 element uses the low log2(SEW) bits of the amount.
Instruction Syntax
vror.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvbbVector Bit Manipulation
Instruction Behavior
VROR.VV is a Zvbb vector rotate-right instruction. Each active element takes data from vs2 and rotates it by the amount from the corresponding vs1 element; only the low log2(SEW) bits of the amount are used.
Quick Understanding & Search Notes
VROR.VV performs a Zvbb rotate right on each active element; the vector operand supplies only the rotate amount and data comes from vs2.
Only the low log2(SEW) bits of the amount are used; no extra rotation beyond SEW is represented.
The vm field is the ordinary V execution mask; the unmasked form may omit it.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vror.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vror.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This is rotate right; shifted-out bits wrap around rather than being discarded.
The rotate amount is truncated to the element width through the low log2(SEW) bits.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
FAQ
How is VROR.VV different from VWSLL?
Rotate keeps the same width and wraps bits; VWSLL is a widening logical left shift with a 2*SEW destination.