Does VROR.VI change element width?
No. The result element width remains the current SEW.
VROR.VI
RISC-V VROR.VI Instruction Details
Instruction ManualVector OP-V (OPIVI)Vector rotate right by immediate amount; each vs2 element uses the low log2(SEW) bits of the amount.
Instruction Syntax
vror.vi vd, vs2, uimm[, v0.t]
Syntax: vror.vi vd, vs2, uimm[, v0.t]; vector registers select v0–v31. uimm is a six-bit unsigned immediate, 0–63. Omitting v0.t selects vm=1; including it selects vm=0.
32-bit OP-V: funct5=01010[31:27], i5=uimm[5][26], vm[25], vs2[24:20], uimm[4:0][19:15], funct3=011, vd[11:7], opcode=1010111.
Available in Zvbb or Zvkb, depending on Zve32x for SEW=8/16/32; 64 additionally requires Zve64x. Rotate each active vs2 element right by the low log2(SEW) bits of uimm; results remain SEW wide.
Enable vector state and use a legal supported vtype. Equal-width sources/destination may overlap and read original values; equal source registers supply equal inputs. LMUL>1 groups must be aligned. With vm=0, vd cannot overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
ZvbbZvkbVector Bit Manipulation
Instruction Behavior
VROR.VI is a Zvbb or Zvkb vector rotate-right instruction. Each active element takes data from vs2 and rotates it by the amount from uimm; only the low log2(SEW) bits of the amount are used.
VROR.VI Decode & Execute Animation
This bounded model shows only lane 0 ISA-visible state; it does not model a pipeline, a cryptographic protocol, or unspecified inactive/tail values.
Execution context: enable the listed extension and vector state, use a legal supported vtype, LMUL=1 and VLEN≥64×SEW. Only lane 0 is expanded; vl=32/64 does not replicate it to other elements. SEW=64 requires Zve64x. Nonzero vstart assumes implementation support; otherwise an illegal-instruction exception is permitted.
Bounded execution context
32-bit OP-V encoding fields
31..27
funct5
01010
26
i5
0
25
vm
1
24..20
vs2
01000
19..15
uimm[4:0]
01011
14..12
OPIVI
011
11..7
vd
00100
6..0
OP-V
1010111
Execution data path
funct5=01010, i5=0, funct3=011, Zvbb/Zvkb
v4[0] <- pending
Quick Understanding & Search Notes
VROR.VI performs a Zvbb/Zvkb rotate right on each active element; the immediate operand supplies only the rotate amount and data comes from vs2.
Available in Zvbb or Zvkb. Zve32x provides SEW=8/16/32; SEW=64 additionally requires Zve64x.
uimm is a six-bit unsigned immediate, 0–63; bit5 occupies inst[26]. Only its low log2(SEW) bits are used.
Omitting v0.t selects vm=1; including v0.t selects vm=0 and active elements using v0.mask[i].
Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements; success resets vstart.
Vector Execution Context
Syntax: vror.vi vd, vs2, uimm[, v0.t]; vector registers select v0–v31. uimm is a six-bit unsigned immediate, 0–63. Omitting v0.t selects vm=1; including it selects vm=0.
32-bit OP-V: funct5=01010[31:27], i5=uimm[5][26], vm[25], vs2[24:20], uimm[4:0][19:15], funct3=011, vd[11:7], opcode=1010111.
Available in Zvbb or Zvkb, depending on Zve32x for SEW=8/16/32; 64 additionally requires Zve64x. Rotate each active vs2 element right by the low log2(SEW) bits of uimm; results remain SEW wide.
Enable vector state and use a legal supported vtype. Equal-width sources/destination may overlap and read original values; equal source registers supply equal inputs. LMUL>1 groups must be aligned. With vm=0, vd cannot overlap v0, which cannot supply both SEW data and an EEW=1 mask.
Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state with legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678, uimm=4: v4[0]=0x81234567. Only active elements/groups are shown; tu keeps tails undisturbed. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state with legal supported vtype, LMUL=1, VLEN=256, vstart=0 and no mask: SEW=32, vl=1, v8[0]=0x12345678, uimm=4: v4[0]=0x81234567. Only active elements/groups are shown; tu keeps tails undisturbed. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vror.vi vd, vs2, uimm[, v0.t]; vector registers select v0–v31. uimm is a six-bit unsigned immediate, 0–63. Omitting v0.t selects vm=1; including it selects vm=0.
- 32-bit OP-V: funct5=01010[31:27], i5=uimm[5][26], vm[25], vs2[24:20], uimm[4:0][19:15], funct3=011, vd[11:7], opcode=1010111.
Semantic Check
- Available in Zvbb or Zvkb, depending on Zve32x for SEW=8/16/32; 64 additionally requires Zve64x. Rotate each active vs2 element right by the low log2(SEW) bits of uimm; results remain SEW wide.
- Enable vector state and use a legal supported vtype. Equal-width sources/destination may overlap and read original values; equal source registers supply equal inputs. LMUL>1 groups must be aligned. With vm=0, vd cannot overlap v0, which cannot supply both SEW data and an EEW=1 mask.
- Enable vector state with a legal supported vtype. Prestart is undisturbed; inactive/tail follow vma/vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support, otherwise an illegal-instruction exception is permitted.
Pitfalls / Common Confusions
This is rotate right; shifted-out bits wrap around rather than being discarded.
The rotate amount is truncated to the element width through the low log2(SEW) bits.
It follows V-extension vl, vstart, vtype, and optional vm mask rules.
FAQ
How is VROR.VI different from VWSLL?
Rotate keeps the same width and wraps bits; VWSLL is a widening logical left shift with a 2*SEW destination.