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VROR.VI

RISC-V VROR.VI Instruction Details

Instruction ManualI-type

Vector rotate right by immediate amount; each vs2 element uses the low log2(SEW) bits of the amount.

Instruction Syntax

vror.vi vd, vs2, uimm, vm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvbbVector Bit Manipulation

Related Search Terms

vror.vi instruction RISC-V vror.vi vror.vi syntax vror.vi encoding vror.vi vector rotate right vror.vi Zvbb vror.vi rotate amount

Instruction Behavior

VROR.VI is a Zvbb vector rotate-right instruction. Each active element takes data from vs2 and rotates it by the amount from uimm; only the low log2(SEW) bits of the amount are used.

Quick Understanding & Search Notes

VROR.VI performs a Zvbb rotate right on each active element; the immediate operand supplies only the rotate amount and data comes from vs2.

Only the low log2(SEW) bits of the amount are used; no extra rotation beyond SEW is represented.

The vm field is the ordinary V execution mask; the unmasked form may omit it.

RISC-V Unprivileged ISA Manual: Vector Cryptography Extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VROR.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vror.vi vd, vs2, imm».

Vector Acceleration

Understand this scenario with real code like «vror.vi vd, vs2, imm».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is I-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This is rotate right; shifted-out bits wrap around rather than being discarded.

The rotate amount is truncated to the element width through the low log2(SEW) bits.

It follows V-extension vl, vstart, vtype, and optional vm mask rules.

FAQ

Does VROR.VI change element width?

No. The result element width remains the current SEW.

How is VROR.VI different from VWSLL?

Rotate keeps the same width and wraps bits; VWSLL is a widening logical left shift with a 2*SEW destination.