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VSEXT.VF8

RISC-V VSEXT.VF8 Instruction Details

Instruction ManualOP-V VXUNARY0 (funct3=010)

VSEXT.VF8 sign-extends EEW=SEW/8 source elements into SEW-wide destination elements.

Instruction Syntax

vsext.vf8 vd, vs2, vm
Operand Breakdown
vs3: source vector register group providing active elements to store.
rs1: integer base-address register; unit-stride forms write consecutive addresses.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerSign-Extend
Related Search Terms
vsext.vf8 instructionvsext.vf8 syntaxvsext.vf8 encodingvsext.vf8 RVVEEW=SEW/8 extensionvector sign-extensionvsext.vf8 v0.t

Instruction Behavior

vsext.vf8 is a RISC-V V-extension vector integer sign-extension instruction. Syntax is `vsext.vf8 vd, vs2, vm`: active vs2 elements are read at EEW=SEW/8 and written as SEW-wide vd elements. Source EMUL is (EEW/SEW)*LMUL; the encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.

VSEXT.VF8 Decode And Execute Animation

Official V-extension integer zero/sign extension from EEW to SEW.

Current step

Show the OP-V encoding

The strip shows opcode, funct6, the VXUNARY0 selector, register fields, and vm.

Live data pathencoding
OP-V
32-bit instruction fields
await read/execute
await result
Syntax: vd, vs2, vm
EEW
8 (SEW/8)
LMUL
m1 (fixed)
VLEN
4096 bits
vstart
0
funct6
010010vm
0vs2
v12vs1 / VXUNARY0
00011funct3
010opcode
1010111
lane 0
vs2: 0x01
waiting
lane 1
vs2: 0x83
masked-off
lane 2
vs2: 0x07
waiting
lane 3
vs2: 0x7F
waiting

Based on the official RISC-V ISA manual. The teaching context assumes the selected SEW/EEW values are supported by the implementation and fixes VLEN=4096, LMUL=m1, and vstart=0; VLMAX=4096/SEW, so the animation's maximum VL of 64 does not exceed VLMAX. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL; this animation offers only SEW choices with a supported EEW.

Quick Understanding & Search Notes

vsext.vf8 processes only active elements within vl: it sign-extends EEW=SEW/8 vs2 elements into SEW-wide vd elements; optional v0.t permits only mask-selected body elements to execute.

Official syntax is `vsext.vf8 vd, vs2, vm`. It has no second vector arithmetic source; the VXUNARY0 selector in the encoding is not an assembly syntax operand.
Source EEW=SEW/8 and source EMUL=(EEW/SEW)*LMUL; destination EEW=SEW and destination EMUL=LMUL. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.
Each active result copies the source top bit into the newly added upper bits, so a source top bit of 1 produces a negative two's-complement result.
Official RISC-V Unprivileged ISA Manual (Vector Integer Extension)

Vector Execution Context

When reading VSEXT.VF8, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vector Integer Extension

Understand this scenario with real code like «vsext.vf8 v8, v12, v0.t».

EEW-to-SEW extension

Understand this scenario with real code like «vsext.vf8 v8, v12, v0.t».

V standard vector extension

Understand this scenario with real code like «vsext.vf8 v8, v12, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is OP-V VXUNARY0 (funct3=010).
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This form reads EEW=SEW/8 source elements, not SEW-wide ones; only the destination elements are SEW wide.
Sign extension copies the source top bit into new upper bits; use the matching vzext form when upper bits must be zero.
Masked-off and tail element values follow the current vtype mask/tail policy; the mnemonic does not imply fixed zeroing.

FAQ

Is VSEXT.VF8 zero extension?

No. VSEXT performs sign extension; zero extension uses VZEXT.VF2/VF4/VF8.