Is VSEXT.VF8 zero extension?
No. VSEXT performs sign extension; zero extension uses VZEXT.VF2/VF4/VF8.
VSEXT.VF8
RISC-V VSEXT.VF8 Instruction Details
Instruction ManualOP-V VXUNARY0 (funct3=010)VSEXT.VF8 sign-extends EEW=SEW/8 source elements into SEW-wide destination elements.
Instruction Syntax
vsext.vf8 vd, vs2, vm
Operand Breakdown
vd is the SEW/LMUL destination group; the sole data source vs2 has EEW=SEW/8 and EMUL=LMUL/8. Active elements copy the source sign bit into new upper bits; this is unary arithmetic without memory access.
32-bit OP-V: funct6=010010, funct3=010, opcode=1010111; vs1 is the fixed VXUNARY0 selector 00011, not a second source. vd/vs2 name v0–v31 group starts.
Source EEW must be supported and source EMUL must not be below the minimum legal LMUL; otherwise the encoding is reserved. A wider destination can overlap only a source with EMUL≥1 located in the highest-numbered part of its group. Legal overlap at different EEWs forces mask/tail agnostic regardless of vma/vta. This m1 demo has source EMUL<1, so overlap is prohibited.
vm denotes optional v0.t; omission means vm=1. Masked vd cannot contain v0; v0 cannot supply both an EEW=1 mask and data at another EEW. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, and without overlap inactive/tail follow vma/vta without guaranteed zeroing.
Require V 1.0, enabled vector state and valid supported vtype. vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart=0. An implementation may reject nonzero vstart values it cannot produce.
VVector IntegerSign-Extend
Instruction Behavior
vsext.vf8 is a RISC-V V-extension vector integer sign-extension instruction. Syntax is `vsext.vf8 vd, vs2, vm`: active vs2 elements are read at EEW=SEW/8 and written as SEW-wide vd elements. Source EMUL is (EEW/SEW)*LMUL; the encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.
VSEXT.VF8 Decode And Execute Animation
Official V-extension integer zero/sign extension from EEW to SEW.
Current step
Show the OP-V encoding
The strip shows opcode, funct6, the VXUNARY0 selector, register fields, and vm.
Live data pathencoding
OP-V
32-bit instruction fields
32-bit instruction fields
→
await read/execute
→
await result
Syntax: vd, vs2, vm
EEW
8 (SEW/8)
8 (SEW/8)
LMUL
m1 (fixed)
m1 (fixed)
VLEN
4096 bits
4096 bits
vstart
0
0
funct6
010010vm
0vs2 [24:20]
01100vs1 / VXUNARY0
00011funct3
010vd [11:7]
01000opcode
1010111
010010vm
0vs2 [24:20]
01100vs1 / VXUNARY0
00011funct3
010vd [11:7]
01000opcode
1010111
lane 0
vs2: 0x01
waiting
vs2: 0x01
waiting
lane 1
vs2: 0x83
masked-off
vs2: 0x83
masked-off
lane 2
vs2: 0x07
waiting
vs2: 0x07
waiting
lane 3
vs2: 0x7F
waiting
vs2: 0x7F
waiting
Based on The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. The teaching context assumes enabled V/vector state, valid vtype, and that the selected SEW/EEW values are supported by the implementation and fixes VLEN=4096, LMUL=m1, and vstart=0; VLMAX=4096/SEW, so the animation's maximum VL of 64 does not exceed VLMAX. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL; this animation assumes supported SEW/EEW and fractional LMUL for every offered choice. Steps explain the ISA, not hardware cycles.
Quick Understanding & Search Notes
vsext.vf8 processes only active elements within vl: it sign-extends EEW=SEW/8 vs2 elements into SEW-wide vd elements; optional v0.t permits only mask-selected body elements to execute.
Official syntax is `vsext.vf8 vd, vs2, vm`. It has no second vector arithmetic source; the VXUNARY0 selector in the encoding is not an assembly syntax operand.
Source EEW=SEW/8 and source EMUL=(EEW/SEW)*LMUL; destination EEW=SEW and destination EMUL=LMUL. The encoding is reserved when source EEW is unsupported or source EMUL is below the minimum legal LMUL.
Active results fill new upper bits with the source sign bit; a set sign bit yields a negative two's-complement value.
Legal source/destination overlap at different EEWs forces mask/tail agnostic regardless of vma/vta.
Vector Execution Context
vd is the SEW/LMUL destination group; the sole data source vs2 has EEW=SEW/8 and EMUL=LMUL/8. Active elements copy the source sign bit into new upper bits; this is unary arithmetic without memory access.
32-bit OP-V: funct6=010010, funct3=010, opcode=1010111; vs1 is the fixed VXUNARY0 selector 00011, not a second source. vd/vs2 name v0–v31 group starts.
Source EEW must be supported and source EMUL must not be below the minimum legal LMUL; otherwise the encoding is reserved. A wider destination can overlap only a source with EMUL≥1 located in the highest-numbered part of its group. Legal overlap at different EEWs forces mask/tail agnostic regardless of vma/vta. This m1 demo has source EMUL<1, so overlap is prohibited.
vm denotes optional v0.t; omission means vm=1. Masked vd cannot contain v0; v0 cannot supply both an EEW=1 mask and data at another EEW. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, and without overlap inactive/tail follow vma/vta without guaranteed zeroing.
Require V 1.0, enabled vector state and valid supported vtype. vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart=0. An implementation may reject nonzero vstart values it cannot produce.
Common Usage Scenarios
Vector Integer Extension
Assume RV32/RV64 V, enabled vector state, valid e64,m1, VLEN≥256, vl=4, vstart=0, supported widths and source EMUL=1/8. v12 holds 8-bit sources [0x01,0x83,0x07,0x7F] and v0.mask=[1,1,0,1]: active v8[0]=1, v8[1]=0xFFFFFFFFFFFFFF83 (−125), v8[3]=127; lane2 follows vma and tails follow vta, without guaranteed zeroing. Success resets vstart=0.
EEW-to-SEW extension
Assume RV32/RV64 V, enabled vector state, valid e64,m1, VLEN≥256, vl=4, vstart=0, supported widths and source EMUL=1/8. v12 holds 8-bit sources [0x01,0x83,0x07,0x7F] and v0.mask=[1,1,0,1]: active v8[0]=1, v8[1]=0xFFFFFFFFFFFFFF83 (−125), v8[3]=127; lane2 follows vma and tails follow vta, without guaranteed zeroing. Success resets vstart=0.
V standard vector extension
Assume RV32/RV64 V, enabled vector state, valid e64,m1, VLEN≥256, vl=4, vstart=0, supported widths and source EMUL=1/8. v12 holds 8-bit sources [0x01,0x83,0x07,0x7F] and v0.mask=[1,1,0,1]: active v8[0]=1, v8[1]=0xFFFFFFFFFFFFFF83 (−125), v8[3]=127; lane2 follows vma and tails follow vta, without guaranteed zeroing. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd is the SEW/LMUL destination group; the sole data source vs2 has EEW=SEW/8 and EMUL=LMUL/8. Active elements copy the source sign bit into new upper bits; this is unary arithmetic without memory access.
- 32-bit OP-V: funct6=010010, funct3=010, opcode=1010111; vs1 is the fixed VXUNARY0 selector 00011, not a second source. vd/vs2 name v0–v31 group starts.
Semantic Check
- Source EEW must be supported and source EMUL must not be below the minimum legal LMUL; otherwise the encoding is reserved. A wider destination can overlap only a source with EMUL≥1 located in the highest-numbered part of its group. Legal overlap at different EEWs forces mask/tail agnostic regardless of vma/vta. This m1 demo has source EMUL<1, so overlap is prohibited.
- vm denotes optional v0.t; omission means vm=1. Masked vd cannot contain v0; v0 cannot supply both an EEW=1 mask and data at another EEW. Active body is vstart≤i<vl with mask enabled; prestart is unchanged, and without overlap inactive/tail follow vma/vta without guaranteed zeroing.
- Require V 1.0, enabled vector state and valid supported vtype. vstart≥vl (including vl=0) updates no destination elements; successful completion resets vstart=0. An implementation may reject nonzero vstart values it cannot produce.
Pitfalls / Common Confusions
This form reads EEW=SEW/8 source elements, not SEW-wide ones; only the destination elements are SEW wide.
Sign extension copies the source top bit into new upper bits; use the matching vzext form when upper bits must be zero.
Without overlap, masked-off and tail elements follow current vma/vta; legal source/destination overlap at different EEWs forces mask/tail agnostic regardless of vma/vta. Agnostic elements may retain old values or become all ones, without guaranteed zeroing.