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VSEXT.VF8

RISC-V VSEXT.VF8 Instruction Details

Instruction ManualR-type

Sign-extend SEW/8 source elements to SEW destination elements.

Instruction Syntax

vsext.vf8 vd, vs2, vm

Operand Breakdown

vs3: source vector register group providing active elements to store.

rs1: integer base-address register; unit-stride forms write consecutive addresses.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

VVector IntegerSign-Extend

Related Search Terms

VSEXT.VF8 instruction vsext.vf8 syntax vector sign extend vsext vf8 RVV extension

Instruction Behavior

VSEXT.VF8 reads narrower signed source elements, sign-extends them to the current SEW width, and writes vd.

Quick Understanding & Search Notes

VSEXT.VF8 promotes a narrow signed integer vector to the current SEW.

Source element width is SEW/8; destination element width is SEW.

The sign bit is extended into the high bits; use VZEXT for unsigned extension.

The destination/source EEW ratio affects legal register-group overlap.

RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSEXT.VF8, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Narrow Data Widening

Understand this scenario with real code like «vsext.vf8 v8, v12, v0.t».

Type Promotion

Understand this scenario with real code like «vsext.vf8 v8, v12, v0.t».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Source EMUL=LMUL/8; can be fractional

Sign bit fill (differs from vzext zero-fill)

FAQ

Is VSEXT.VF8 zero extension?

No. VSEXT performs sign extension; zero extension uses VZEXT.VF2/VF4/VF8.