Where does vslide1up.vx insert the scalar?
Insert only when vd[0] is active; if masked off, it follows vma. Other active elements take vs2[i-1]. The destination is unchanged when vstart>=vl or vl=0.
VSLIDE1UP.VX
RISC-V VSLIDE1UP.VX Instruction Details
Instruction ManualV-typeSlide vector elements toward higher indexes and insert a scalar.
Instruction Syntax
vslide1up.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies the inserted scalar: sign-extend for XLEN<SEW and take low SEW bits for XLEN>SEW; x0 supplies zero.
32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=110 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Only active destinations update: vd[0]=x[rs1]; for i>0, vd[i]=vs2[i-1]. No memory access.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
VVector PermutationSlide
Instruction Behavior
VSLIDE1UP.VX copies adjacent vs2 elements to active destinations and inserts x[rs1] into vd[0] only when that destination is active. Inactive/tail elements follow vma/vta.
VSLIDE1UP.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDE1UP inserts scalar x[rs1] into vd[0] and moves vs2 elements one position toward higher indexes.
Instruction input
vslide1up.vx
Require V 1.0, enabled vector state, and valid supported vtype/SEW. Fix LMUL=m1 and vstart=0; this teaching configuration has VLEN=VLMAX×SEW=256, at least 128 bits. Changing SEW/VLMAX switches configurations. Only body is shown; inactive/tail values follow vma/vta without definite values. VL=0 updates no destination elements, including tails. With masking, vd/vs2 cannot be v0. vd must not overlap vs2. Inserted scalars sign-extend when XLEN<SEW and take low bits when XLEN>SEW; x0 supplies zero. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvslide1up.vx
funct6
001110
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i-1
i-1
i-1
i-1
i-1
i-1
i-1
i-1
x11
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslide1up.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide one up with scalar insert, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslide1up.vx is the fixed OFFSET=1 slideup variant: active vd[0] receives x[rs1], and active vd[i>0] reads vs2[i-1].
OP-V encoding uses funct6=001110 and funct3=110 for vslide1up.vx.
Insert x[rs1] into vd[0] only when that element is active; sign-extend for XLEN<SEW and take low bits for XLEN>SEW.
The destination vector register group cannot overlap the source vector register group.
Require an enabled vector extension/state, valid vtype, and supported SEW. When vstart>=vl (including vl=0), the entire destination is unchanged. Active elements satisfy vstart<=i<vl and are mask-enabled; inactive/tail elements follow vma/vta.
Omitting the mask operand selects vm=1; v0.t selects vm=0 and the v0 bit at each destination index. A masked vd cannot overlap v0, and v0 cannot also supply SEW data.
Vector Execution Context
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies the inserted scalar: sign-extend for XLEN<SEW and take low SEW bits for XLEN>SEW; x0 supplies zero.
32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=110 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Only active destinations update: vd[0]=x[rs1]; for i>0, vd[i]=vs2[i-1]. No memory access.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Common Usage Scenarios
Register element rearrangement
Understand this scenario with real code like «vslide1up.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies the inserted scalar: sign-extend for XLEN<SEW and take low SEW bits for XLEN>SEW; x0 supplies zero.
- 32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=110 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Semantic Check
- Only active destinations update: vd[0]=x[rs1]; for i>0, vd[i]=vs2[i-1]. No memory access.
- Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Pitfalls / Common Confusions
The destination vector register group cannot overlap the source group.
The scalar x[rs1] is inserted into vd[0] only when that element is active.
The scalar sign-extends to SEW when XLEN<SEW; when XLEN>SEW, only the low SEW bits are copied.
FAQ
Does VSLIDE1UP.VX access memory?
No. It only rearranges vector-register elements or inserts a scalar-register value; memory loads and stores are handled by vector load/store instructions.