Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSLIDE1UP.VX
RISC-V VSLIDE1UP.VX Instruction Details
Instruction ManualR-typeSlide vector elements toward higher indexes and insert a scalar.
Instruction Syntax
vslide1up.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationSlide
Instruction Behavior
VSLIDE1UP.VX moves vs2 elements by offset 1 toward higher indexes into vd. The boundary element is filled from scalar x[rs1].
VSLIDE1UP.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDE1UP inserts scalar x[rs1] into vd[0] and moves vs2 elements one position toward higher indexes.
Instruction input
vslide1up.vx
OP-V encodingvslide1up.vx
funct6
001110
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i-1
i-1
i-1
i-1
i-1
i-1
i-1
i-1
x11
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
0x0055
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslide1up.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide one up with scalar insert, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslide1up.vx is the fixed OFFSET=1 slideup variant: active vd[0] receives x[rs1], and active vd[i>0] reads vs2[i-1].
OP-V encoding uses funct6=001110 and funct3=110 for vslide1up.vx.
x[rs1] is inserted into vd[0], not vd[vl-1].
The destination vector register group cannot overlap the source vector register group.
Vector Execution Context
When reading VSLIDE1UP.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Shift
Understand this scenario with real code like «vslide1up.vx v8, v12, x5, v0.t».
Convolution
Understand this scenario with real code like «vslide1up.vx v8, v12, x5, v0.t».
Shift Register
Understand this scenario with real code like «vslide1up.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The destination vector register group cannot overlap the source group.
The scalar x[rs1] is inserted at vd[0].
When XLEN and SEW differ, the inserted scalar is sign-extended or low-bit truncated by the official rule.
FAQ
Where does vslide1up.vx insert the scalar?
It inserts into active vd[0]. Other active elements take the previous lower-numbered source element vs2[i-1].
Does VSLIDE1UP.VX access memory?
No. It only rearranges vector-register elements or inserts a scalar-register value; memory loads and stores are handled by vector load/store instructions.