Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSLIDEUP.VX
RISC-V VSLIDEUP.VX Instruction Details
Instruction ManualR-typeSlide vector elements toward higher indexes.
Instruction Syntax
vslideup.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationSlide
Instruction Behavior
VSLIDEUP.VX moves vs2 elements by offset x[rs1] toward higher indexes into vd. Destination elements below the offset are unchanged; other active elements are taken from lower-numbered source elements.
VSLIDEUP.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDEUP reads lower-numbered source elements by OFFSET; destination elements below OFFSET keep old vd values.
Instruction input
vslideup.vx
OP-V encodingvslideup.vx
funct6
001110
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0x0080
0x0081
0x0082
0x0083
0x0084
0x0085
0x0086
0x0087
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
x11
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslideup.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide up, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslideup.vx reads OFFSET from x[rs1]; active element i keeps old vd[i] if i < OFFSET, otherwise it reads vs2[i-OFFSET].
OP-V encoding uses funct6=001110 and funct3=100 for vslideup.vx.
OFFSET comes from x[rs1] and is not truncated to SEW when XLEN is larger than SEW.
The destination vector register group cannot overlap the source vector register group.
Vector Execution Context
When reading VSLIDEUP.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Shift
Understand this scenario with real code like «vslideup.vx v8, v12, x5, v0.t».
Convolution
Understand this scenario with real code like «vslideup.vx v8, v12, x5, v0.t».
Shift Register
Understand this scenario with real code like «vslideup.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The destination vector register group cannot overlap the source group.
OFFSET comes from x[rs1]; when XLEN>SEW it is not truncated to SEW.
Destination elements 0..OFFSET-1 remain unchanged.
FAQ
Is x[rs1] truncated to SEW for vslideup.vx?
No. The official rule uses x[rs1] as an XLEN-wide OFFSET; this differs from ordinary .vx arithmetic that converts a scalar into a SEW-width element.
Does VSLIDEUP.VX access memory?
No. It only rearranges vector-register elements or inserts a scalar-register value; memory loads and stores are handled by vector load/store instructions.