Is x[rs1] truncated to SEW for vslideup.vx?
No. OFFSET uses all unsigned XLEN bits of x[rs1], without conversion to SEW.
VSLIDEUP.VX
RISC-V VSLIDEUP.VX Instruction Details
Instruction ManualOPIVXSlide vector elements toward higher indexes.
Instruction Syntax
vslideup.vx vd, vs2, rs1, vm
Operand Breakdown
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Destinations i<min(vl,max(vstart,OFFSET)) remain unchanged; remaining active vd[i]=vs2[i-OFFSET]. This rearranges elements rather than shifting bits within each element.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
VVector PermutationSlide
Instruction Behavior
VSLIDEUP.VX moves vs2 elements by offset x[rs1] toward higher indexes into vd. Destination elements below the offset are unchanged; other active elements are taken from lower-numbered source elements.
VSLIDEUP.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDEUP reads lower-numbered source elements by OFFSET; destination elements below OFFSET keep old vd values.
Instruction input
vslideup.vx
Require V 1.0, enabled vector state, and valid supported vtype/SEW. Fix LMUL=m1 and vstart=0; this teaching configuration has VLEN=VLMAX×SEW=256, at least 128 bits. Changing SEW/VLMAX switches configurations. Only body is shown; inactive/tail values follow vma/vta without definite values. VL=0 updates no destination elements, including tails. With masking, vd/vs2 cannot be v0. vd must not overlap vs2. Destinations below OFFSET and below vl keep their old values. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvslideup.vx
funct6
001110
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
old v4
0x0080
0x0081
0x0082
0x0083
0x0084
0x0085
0x0086
0x0087
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
i-OFF
x11
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslideup.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide up, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
With vstart=0, destinations i<min(OFFSET,vl) stay unchanged; for OFFSET≤i<vl with the mask enabled, vd[i]=vs2[i-OFFSET].
OP-V encoding uses funct6=001110 and funct3=100 for vslideup.vx.
OFFSET comes from x[rs1] and is not truncated to SEW when XLEN is larger than SEW.
The destination vector register group cannot overlap the source vector register group.
Write only enabled destinations max(vstart,OFFSET)≤i<vl; vstart≥vl leaves vd unchanged, and inactive/tail elements follow vma/vta.
Vector Execution Context
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Destinations i<min(vl,max(vstart,OFFSET)) remain unchanged; remaining active vd[i]=vs2[i-OFFSET]. This rearranges elements rather than shifting bits within each element.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Common Usage Scenarios
Rearrange elements by scalar offset
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with every body mask bit enabled. SEW=8, vl=4, x5=2, old v8=[90,91,92,93], v12=[10,20,30,40] → v8=[90,91,10,20]. Inactive/tail follow vma/vta; success resets vstart=0.
Preserve low-index destination elements
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with every body mask bit enabled. SEW=8, vl=4, x5=2, old v8=[90,91,92,93], v12=[10,20,30,40] → v8=[90,91,10,20]. Inactive/tail follow vma/vta; success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. The two groups must not overlap; overlap is reserved. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
- 32-bit OP-V: funct6=001110 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Semantic Check
- Destinations i<min(vl,max(vstart,OFFSET)) remain unchanged; remaining active vd[i]=vs2[i-OFFSET]. This rearranges elements rather than shifting bits within each element.
- Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Pitfalls / Common Confusions
Overlapping vd and vs2 groups are reserved.
OFFSET is the full unsigned XLEN value, not truncated to SEW.
Only destinations i<min(OFFSET,vl) retain old values; tails still follow vta.
FAQ
Does VSLIDEUP.VX access memory?
No. It rearranges vector registers; x[rs1] supplies OFFSET.