Is the vslidedown.vx OFFSET an element count or byte count?
It is an element-index offset, not a byte offset; lane i reads vs2[i+OFFSET].
VSLIDEDOWN.VX
RISC-V VSLIDEDOWN.VX Instruction Details
Instruction ManualV-typeSlide vector elements toward lower indexes.
Instruction Syntax
vslidedown.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
VVector PermutationSlide
Instruction Behavior
VSLIDEDOWN.VX moves vs2 elements by offset x[rs1] toward lower indexes into vd. A source index outside VLMAX writes zero to the destination element.
VSLIDEDOWN.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDEDOWN reads higher-numbered source elements by OFFSET; destination elements whose source index is >= VLMAX receive zero.
Instruction input
vslidedown.vx
Require V 1.0, enabled vector state, and valid supported vtype/SEW. Fix LMUL=m1 and vstart=0; this teaching configuration has VLEN=VLMAX×SEW=256, at least 128 bits. Changing SEW/VLMAX switches configurations. Only body is shown; inactive/tail values follow vma/vta without definite values. VL=0 updates no destination elements, including tails. With masking, vd/vs2 cannot be v0. Equal-width vd/vs2 may overlap. OFFSET is a full unsigned XLEN value or zero-extended 5-bit immediate; source indexes ≥VLMAX return zero. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvslidedown.vx
funct6
001111
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
x11
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslidedown.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide down, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslidedown.vx reads OFFSET from x[rs1]; active element i reads vs2[i+OFFSET], or writes zero if the source index is greater than or equal to VLMAX.
OP-V encoding uses funct6=001111 and funct3=100 for vslidedown.vx.
OFFSET comes from x[rs1] and is not truncated to SEW when XLEN is larger than SEW.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.
Require an enabled vector extension/state, valid vtype, and supported SEW. When vstart>=vl (including vl=0), the entire destination is unchanged. Active elements satisfy vstart<=i<vl and are mask-enabled; inactive/tail elements follow vma/vta.
Omitting the mask operand selects vm=1; v0.t selects vm=0 and the v0 bit at each destination index. A masked vd cannot overlap v0, and v0 cannot also supply SEW data.
OFFSET is an unsigned element-index offset, not bytes: x[rs1] uses full XLEN and uimm is 0..31. Source elements beyond vl but below VLMAX may be read; zero fill starts at source index VLMAX.
Vector Execution Context
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Common Usage Scenarios
Register element rearrangement
Understand this scenario with real code like «vslidedown.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. rs1 supplies a full unsigned XLEN element offset without SEW truncation; x0 supplies offset zero.
- 32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, rs1 at bits19:15, funct3=100 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Semantic Check
- Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.
- Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
Pitfalls / Common Confusions
OFFSET is the full unsigned XLEN value in x[rs1]; it is not truncated to SEW when XLEN>SEW.
For active destinations only, i+OFFSET>=VLMAX writes zero; inactive/tail elements follow vma/vta.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.
FAQ
Does VSLIDEDOWN.VX access memory?
No. It rearranges elements within vector register groups and performs no memory load or store.