Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSLIDEDOWN.VX
RISC-V VSLIDEDOWN.VX Instruction Details
Instruction ManualR-typeSlide vector elements toward lower indexes.
Instruction Syntax
vslidedown.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationSlide
Instruction Behavior
VSLIDEDOWN.VX moves vs2 elements by offset x[rs1] toward lower indexes into vd. A source index outside VLMAX writes zero to the destination element.
VSLIDEDOWN.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDEDOWN reads higher-numbered source elements by OFFSET; destination elements whose source index is >= VLMAX receive zero.
Instruction input
vslidedown.vx
OP-V encodingvslidedown.vx
funct6
001111
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
x11
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslidedown.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide down, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslidedown.vx reads OFFSET from x[rs1]; active element i reads vs2[i+OFFSET], or writes zero if the source index is greater than or equal to VLMAX.
OP-V encoding uses funct6=001111 and funct3=100 for vslidedown.vx.
OFFSET comes from x[rs1] and is not truncated to SEW when XLEN is larger than SEW.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.
Vector Execution Context
When reading VSLIDEDOWN.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Shift
Understand this scenario with real code like «vslidedown.vx v8, v12, x5, v0.t».
Convolution
Understand this scenario with real code like «vslidedown.vx v8, v12, x5, v0.t».
Shift Register
Understand this scenario with real code like «vslidedown.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
OFFSET comes from x[rs1]; when XLEN>SEW it is not truncated to SEW.
When i+OFFSET >= VLMAX, the result element is zero.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.
FAQ
Is the vslidedown.vx OFFSET an element count or byte count?
It is an element-index offset, not a byte offset; lane i reads vs2[i+OFFSET].
Does VSLIDEDOWN.VX access memory?
No. It only rearranges vector-register elements or inserts a scalar-register value; memory loads and stores are handled by vector load/store instructions.