Is VSM4K.VI an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
VSM4K.VI
RISC-V VSM4K.VI Instruction Details
Instruction ManualV-type (OP-VE / OPMVV)Vector SM4 key expansion: uimm[2:0] selects a round group and generates the next four round keys.
Instruction Syntax
vsm4k.vi vd, vs2, uimm
Syntax: vsm4k.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=100001[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksed depends on Zve32x with SEW=32 only. vs2 supplies four round keys; uimm[2:0] selects the CK group and uimm[4:3] is ignored. S-box substitution and rotations by 13/23 generate the next four keys; vd is output only. Braces run from highest to lowest element index.
EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. No extra vd/vs2 overlap prohibition; equal sources read the same original values. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
ZvksedVector CryptoSM4
Instruction Behavior
Generate four SM4 round keys from vs2 into vd. uimm[2:0] selects the group; uimm[4:3] is ignored. SEW=32, EGW=128, EGS=4.
VSM4K.VI Decode & Execute Animation
This bounded model shows official ISA-visible data flow for one element group; it does not model a cryptographic protocol or microarchitecture.
vsm4k.vi
Fixed vm=1, OP-VE, OPMVV; EGS=4, EGW=128.
Lists below run from low to high element index; only the active group is shown and tu preserves tails. vs2[rk0..rk3]=[0,1,2,3].
funct6=100001vm=1vs2=01000uimm=00000OPMVV=010vd=00100OP-VE=1110111
Execution data path
OP-VE -> funct6 100001 -> vsm4k.vi
result pending
Quick Understanding & Search Notes
VSM4K.VI is an SM4 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
VSM4K.VI uses 128-bit element groups; uimm[2:0] selects the round group and uimm[4:3] is ignored.
The official syntax has no vm operand, so v0.t masking is not added.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 33: Vector Cryptography Extensions, Version 1.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31: V Standard Extension for Vector Operations, Version 1.0
Vector Execution Context
Syntax: vsm4k.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=100001[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksed depends on Zve32x with SEW=32 only. vs2 supplies four round keys; uimm[2:0] selects the CK group and uimm[4:3] is ignored. S-box substitution and rotations by 13/23 generate the next four keys; vd is output only. Braces run from highest to lowest element index.
EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. No extra vd/vs2 overlap prohibition; equal sources read the same original values. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. The example uses uimm=0. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. The example uses uimm=0. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsm4k.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
- 32-bit OP-VE: funct6=100001[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Semantic Check
- Zvksed depends on Zve32x with SEW=32 only. vs2 supplies four round keys; uimm[2:0] selects the CK group and uimm[4:3] is ignored. S-box substitution and rotations by 13/23 generate the next four keys; vd is output only. Braces run from highest to lowest element index.
- EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. No extra vd/vs2 overlap prohibition; equal sources read the same original values. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
- Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=4.
uimm[2:0] is the round-group number, uimm[4:3] is ignored, and this instruction has no additional vd/vs2 overlap-reserved condition.
FAQ
What vtype restriction matters for VSM4K.VI?
SEW must be 32 and LMUL*VLEN must cover a 128-bit element group.