Is VSM4R.VS an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
VSM4R.VS
RISC-V VSM4R.VS Instruction Details
Instruction ManualV-type (OP-VE / OPMVV)Vector four SM4 encryption/decryption rounds; executes as an unmasked element-group crypto instruction.
Instruction Syntax
vsm4r.vs vd, vs2
Syntax: vsm4r.vs vd, vs2; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101001[31:26], vm=1[25], vs2[24:20], fixed 10000[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksed depends on Zve32x with SEW=32 only. vd supplies four state words; scalar element group 0 in vs2 supplies four round keys shared by all active vd groups. Write vd after four rounds; decryption supplies round keys in reverse order. Braces run from highest to lowest element index.
EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
ZvksedVector CryptoSM4
Instruction Behavior
Perform four SM4 rounds on each vd state group using the shared vs2 key group 0. SEW=32, EGW=128, EGS=4.
VSM4R.VS Decode & Execute Animation
This bounded model shows official ISA-visible data flow for one element group; it does not model a cryptographic protocol or microarchitecture.
vsm4r.vs
Fixed vm=1, OP-VE, OPMVV; EGS=4, EGW=128.
Lists below run from low to high element index; only the active group is shown and tu preserves tails. vd[x0..x3]=[0,1,2,3]; vs2[rk0..rk3]=[4,5,6,7]. .vs reads scalar element group 0 from vs2.
funct6=101001vm=1vs2=01000vs1=10000OPMVV=010vd=00100OP-VE=1110111
Execution data path
OP-VE -> funct6 101001 -> vsm4r.vs
result pending
Quick Understanding & Search Notes
VSM4R.VS is an SM4 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
SM4 uses 128-bit element groups; the .vs form takes one scalar element group from vs2.
The official syntax has no vm operand, so v0.t masking is not added.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 33: Vector Cryptography Extensions, Version 1.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31: V Standard Extension for Vector Operations, Version 1.0
Vector Execution Context
Syntax: vsm4r.vs vd, vs2; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101001[31:26], vm=1[25], vs2[24:20], fixed 10000[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksed depends on Zve32x with SEW=32 only. vd supplies four state words; scalar element group 0 in vs2 supplies four round keys shared by all active vd groups. Write vd after four rounds; decryption supplies round keys in reverse order. Braces run from highest to lowest element index.
EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsm4r.vs vd, vs2; v0–v31 are vector registers; no immediate. Fixed vm=1; no v0.t masking.
- 32-bit OP-VE: funct6=101001[31:26], vm=1[25], vs2[24:20], fixed 10000[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Semantic Check
- Zvksed depends on Zve32x with SEW=32 only. vd supplies four state words; scalar element group 0 in vs2 supplies four round keys shared by all active vd groups. Write vd after four rounds; decryption supplies round keys in reverse order. Braces run from highest to lowest element index.
- EGS=4, EGW=128. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
- Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=4.
The .vs vs2 operand is a scalar element group in a vector register, and vd must not overlap vs2.
FAQ
What vtype restriction matters for VSM4R.VS?
SEW must be 32 and LMUL*VLEN must cover a 128-bit element group.