Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSM4R.VS
RISC-V VSM4R.VS Instruction Details
Instruction ManualR-typeVector four SM4 encryption/decryption rounds; executes as an unmasked element-group crypto instruction.
Instruction Syntax
vsm4r.vs vd, vs2
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvksedVector CryptoSM4
Instruction Behavior
VSM4R.VS is a vector four SM4 encryption/decryption rounds instruction. SM4 forms use SEW=32, EGW=128, and EGS=4. In the .vs form, the scalar operand is a 128-bit element group in vs2, not a GPR scalar.
Quick Understanding & Search Notes
VSM4R.VS is an SM4 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
SM4 uses 128-bit element groups; the .vs form takes one scalar element group from vs2.
The official syntax has no vm operand, so v0.t masking is not added.
Vector Execution Context
When reading VSM4R.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vsm4r.vs vd, vs2».
Vector Acceleration
Understand this scenario with real code like «vsm4r.vs vd, vs2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=4.
The .vs vs2 operand is a scalar element group in a vector register, and vd must not overlap vs2.
FAQ
Is VSM4R.VS an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
What vtype restriction matters for VSM4R.VS?
SEW must be 32 and LMUL*VLEN must cover a 128-bit element group.