Is VSM4R.VV an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
VSM4R.VV
RISC-V VSM4R.VV Instruction Details
Instruction ManualV-type (OP-VE / OPMVV)Performs four SM4 rounds on each active 128-bit state group using the corresponding vector round-key group.
Instruction Syntax
vsm4r.vv vd, vs2
Syntax: vsm4r.vv vd, vs2; vd supplies four current-state words and receives the next state; the corresponding vs2 group supplies four round keys. Registers are v0–v31; no v0.t operand.
32-bit OP-VE: funct6=101000, vm=1, fixed vs1 field=10000, OPMVV=010, opcode=1110111. Zvksed depends on Zve32x.
Perform four rounds: B=x1 XOR x2 XOR x3 XOR rk; S=byte-wise SM4 S-box(B); next word=x0 XOR S XOR ROL32(S,2/10/18/24). Decryption supplies keys in reverse order.
SEW=32, EGS=4, EGW=128. vl/vstart not divisible by four or other SEWs are reserved. LMUL*VLEN<128 raises illegal-instruction even at vl=0. Equal-width vd/vs2 overlap reads original values; groups follow LMUL alignment.
Require enabled vector state and valid vtype. Process active groups only; preserve prestart and apply vta to tails. vstart≥vl changes no destination; success clears vstart. Nonzero vstart assumes implementation support. Execution latency must be data-independent.
ZvksedVector CryptoSM4
Instruction Behavior
VSM4R.VV performs four SM4 rounds, reading four state words from vd and four round keys from the corresponding vs2 group, then replacing vd. SEW=32, EGS=4, EGW=128; vm=1 is fixed. Decryption supplies keys in reverse order.
VSM4R.VV Decode & Execute Animation
This bounded model shows official ISA-visible data flow for one element group; it does not model a cryptographic protocol or microarchitecture.
vsm4r.vv
Fixed vm=1, OP-VE, OPMVV; EGS=4, EGW=128.
Lists below run from low to high element index; only the active group is shown and tu preserves tails. vd[x0..x3]=[0,1,2,3]; vs2[rk0..rk3]=[4,5,6,7]. .vv reads the vs2 round-key group corresponding to the current vd state group.
funct6=101000vm=1vs2=01000vs1=10000OPMVV=010vd=00100OP-VE=1110111
Execution data path
OP-VE -> funct6 101000 -> vsm4r.vv
result pending
Quick Understanding & Search Notes
VSM4R.VV is an SM4 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
32-bit OP-VE: funct6=101000, vm=1, vs1=10000, funct3=010 (OPMVV), opcode=1110111. vd reads and writes state; vs2 supplies corresponding keys. Equal-width vd/vs2 overlap reads original values.
Zvksed requires Zve32x. SEW≠32 or vl/vstart not divisible by four are reserved. LMUL*VLEN<128 traps even at vl=0. Groups follow LMUL alignment.
Require enabled vector state and valid vtype. Process vstart/4≤i<vl/4; prestart stays, tails follow vta. vstart≥vl updates nothing; success clears vstart. Latency must be data-independent.
Vector Execution Context
Syntax: vsm4r.vv vd, vs2; vd supplies four current-state words and receives the next state; the corresponding vs2 group supplies four round keys. Registers are v0–v31; no v0.t operand.
32-bit OP-VE: funct6=101000, vm=1, fixed vs1 field=10000, OPMVV=010, opcode=1110111. Zvksed depends on Zve32x.
Perform four rounds: B=x1 XOR x2 XOR x3 XOR rk; S=byte-wise SM4 S-box(B); next word=x0 XOR S XOR ROL32(S,2/10/18/24). Decryption supplies keys in reverse order.
SEW=32, EGS=4, EGW=128. vl/vstart not divisible by four or other SEWs are reserved. LMUL*VLEN<128 raises illegal-instruction even at vl=0. Equal-width vd/vs2 overlap reads original values; groups follow LMUL alignment.
Require enabled vector state and valid vtype. Process active groups only; preserve prestart and apply vta to tails. vstart≥vl changes no destination; success clears vstart. Nonzero vstart assumes implementation support. Execution latency must be data-independent.
Common Usage Scenarios
Four SM4 rounds
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Vector round keys
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=4, vstart=0 and tu. Initialize the input groups named in the syntax. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsm4r.vv vd, vs2; vd supplies four current-state words and receives the next state; the corresponding vs2 group supplies four round keys. Registers are v0–v31; no v0.t operand.
- 32-bit OP-VE: funct6=101000, vm=1, fixed vs1 field=10000, OPMVV=010, opcode=1110111. Zvksed depends on Zve32x.
Semantic Check
- Perform four rounds: B=x1 XOR x2 XOR x3 XOR rk; S=byte-wise SM4 S-box(B); next word=x0 XOR S XOR ROL32(S,2/10/18/24). Decryption supplies keys in reverse order.
- SEW=32, EGS=4, EGW=128. vl/vstart not divisible by four or other SEWs are reserved. LMUL*VLEN<128 raises illegal-instruction even at vl=0. Equal-width vd/vs2 overlap reads original values; groups follow LMUL alignment.
- Require enabled vector state and valid vtype. Process active groups only; preserve prestart and apply vta to tails. vstart≥vl changes no destination; success clears vstart. Nonzero vstart assumes implementation support. Execution latency must be data-independent.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=4.
VSM4R.VV allows vd/vs2 overlap; only .vs reserves it.
FAQ
What vtype restriction matters for VSM4R.VV?
SEW must be 32 and LMUL*VLEN must cover a 128-bit element group.