VWADDU.VX

RISC-V VWADDU.VX Instruction Details

Q: How is VWADDU.VX different from ordinary addition?

VWADDU.VX zero-extends the SEW-wide vs2 value and extends the XLEN/SEW-converted SEW bit pattern from x[rs1] as unsigned to produce a 2*SEW-wide result; ordinary single-width vector addition writes only a SEW-wide result.

Q: Does VWADDU.VX read old vd as an accumulator?

No. These .vv/.vx forms write a result formed from current SEW-wide sources; .wv/.wx are wide-vs2-source forms and likewise do not read old vd.

Instruction ManualV-type

VWADDU.VX performs unsigned widening add; SEW source elements are zero-extended and written as 2*SEW-wide results.

Instruction Syntax

vwaddu.vx vd, vs2, rs1, vm

Operand Breakdown

vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 has EEW=SEW and EMUL=LMUL. rs1 is an integer scalar: take low SEW bits for XLEN>SEW or first sign-extend to SEW for XLEN<SEW, including unsigned addition; x0 supplies zero.

32-bit OP-V: opcode=1010111, funct6=110000, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. The syntax's final vm denotes optional v0.t; omission is unmasked.

For active elements, zero-extend both SEW sources to 2*SEW before adding them; keep low 2*SEW result bits. No old-vd accumulation, saturation or vxsat change. Equal sources read equal initial values. Group starts align to EMUL. Wide vd may overlap a narrow source only when source EMUL>=1 and their highest registers match; legal different-EEW overlap forces mask/tail agnostic.

Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. vm=0 uses v0.t; vm=1 is unmasked. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.

VVector Operations

Extension condition: Requires RV32/RV64 V 1.0, enabled vector state, vill=0, and support for the selected SEW and 2*SEW element widths; widening SEW=64 needs 128-bit integer element support.

Related Search Terms

vwaddu.vx instruction vwaddu.vx syntax vwaddu.vx encoding unsigned widening add RVV widening vwaddu.vx mask

Instruction Behavior

vwaddu.vx is a RISC-V V extension vector-scalar unsigned widening add instruction. For active elements, the SEW-wide vs2 value is zero-extended; x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule, then is zero-extended as an unsigned value to 2*SEW; the values are added and written to the 2*SEW-wide vd destination.

VWADDU.VX Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VWADDU zero-extends SEW source elements before writing 2*SEW-wide add results to vd.

Instruction input

vwaddu.vx

vdUse an even start; wide vd has EMUL=2; a narrow overlap must be the highest registervs2Use v1-v31; v0 supplies the EEW=1 execution maskrs1Use x0-x31 or ABI namevmexecution mask control

Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096 and vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer element support. Enter nonnegative bit patterns: 16-bit vs2 and 16-bit second source. Zero-extend the unsigned narrow source before addition; keep the low 32 result bits. Scalars first follow XLEN/SEW conversion: take low bits when XLEN>SEW and sign-extend when XLEN<SEW, including unsigned addition; x0 supplies zero. Equal sources require equal initial values. With v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values; Wide vd has EMUL=2 and an even start; a narrow source can overlap vd only at the destination group’s highest register, forcing agnostic behavior at different EEWs. VL=0 leaves vd unchanged; success resets vstart=0 and leaves vxsat unchanged. Stages are not processor cycles.

Execution Context

VLSEWXLENvs2 elementscomma-separatedx11 valueXLEN=64, converted to SEW by .vx rulesv0 mask bitscontinuous 0/1 bit string

OP-V encodingvwaddu.vx

funct6

110000

vs2

01000

rs1

01011

funct3

110

00100

opcode

1010111

lane

0x00fa

0x010b

0x011c

0x012d

0x013e

0x014f

0x0160

0x0171

x11

0x0013

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vwaddu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VWADDU.VX is not ordinary SEW-wrapping addition: vs2 is zero-extended, while x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule and is then extended as unsigned; the result is kept in a 2*SEW-wide destination element.

Official syntax is `vwaddu.vx vd, vs2, rs1, vm`; vm=1 is unmasked, while vm=0 uses v0.t to select active elements for this instruction.

vs2 is SEW-wide and zero-extended to 2*SEW; for .vx, x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule, then is zero-extended as an unsigned value before addition.

Destination elements are 2*SEW wide and destination EMUL is twice the source EMUL; this is not an accumulator instruction that reads old vd.

Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply fixed zeroing.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — V 1.0, §31.5, §31.10–31.11, §31.20

Vector Execution Context

When reading VWADDU.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Vector Integer Arithmetic

Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; SEW=8, v12=[255,127,0,255], x5=1. v8=[0x0100,0x0080,unchanged,0x0100]; zero-extend unsigned narrow sources, keeping low 16 result bits. Lane2 and tails keep old values; vxsat stays unchanged. Success resets vstart=0.

Widening Operations

Vectorized Loops

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is V-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Destination elements are 2*SEW wide, so the destination register group EMUL widens too.

Unsigned forms zero-extend inputs.

This is widening addition, not saturating addition; it does not set vxsat.

FAQ

How is VWADDU.VX different from ordinary addition?