Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWADDU.VX
RISC-V VWADDU.VX Instruction Details
Instruction ManualV-typeVWADDU.VX performs unsigned widening add; SEW source elements are zero-extended and written as 2*SEW-wide results.
Instruction Syntax
vwaddu.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
vwaddu.vx is a RISC-V V extension vector-scalar unsigned widening add instruction. For active elements, the SEW-wide vs2 value is zero-extended; x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule, then is zero-extended as an unsigned value to 2*SEW; the values are added and written to the 2*SEW-wide vd destination.
VWADDU.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWADDU zero-extends SEW source elements before writing 2*SEW-wide add results to vd.
Instruction input
vwaddu.vx
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. The wide vd destination has EMUL=2 and must start at an even register; if it overlaps a SEW source, that source must be the highest-numbered register in the destination group. Such a legal different-EEW overlap is mask- and tail-agnostic regardless of vtype.vma/vta.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvwaddu.vx
funct6
110000
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
w+
w+
w+
w+
w+
w+
w+
w+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwaddu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWADDU.VX is not ordinary SEW-wrapping addition: vs2 is zero-extended, while x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule and is then extended as unsigned; the result is kept in a 2*SEW-wide destination element.
Official syntax is `vwaddu.vx vd, vs2, rs1, vm`; vm=1 is unmasked, while vm=0 uses v0.t to select active elements for this instruction.
vs2 is SEW-wide and zero-extended to 2*SEW; for .vx, x[rs1] first becomes an SEW bit pattern under the XLEN/SEW rule, then is zero-extended as an unsigned value before addition.
Destination elements are 2*SEW wide and destination EMUL is twice the source EMUL; this is not an accumulator instruction that reads old vd.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply fixed zeroing.
Vector Execution Context
When reading VWADDU.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Integer Arithmetic
Understand this scenario with real code like «vwaddu.vx v8, v12, x5, v0.t».
Widening Operations
Understand this scenario with real code like «vwaddu.vx v8, v12, x5, v0.t».
Vectorized Loops
Understand this scenario with real code like «vwaddu.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Destination elements are 2*SEW wide, so the destination register group EMUL widens too.
Unsigned forms zero-extend inputs.
This is widening addition, not saturating addition; it does not set vxsat.
FAQ
How is VWADDU.VX different from ordinary addition?
VWADDU.VX zero-extends the SEW-wide vs2 value and extends the XLEN/SEW-converted SEW bit pattern from x[rs1] as unsigned to produce a 2*SEW-wide result; ordinary single-width vector addition writes only a SEW-wide result.
Does VWADDU.VX read old vd as an accumulator?
No. These .vv/.vx forms write a result formed from current SEW-wide sources; .wv/.wx are wide-vs2-source forms and likewise do not read old vd.