Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWADDU.WX
RISC-V VWADDU.WX Instruction Details
Instruction ManualV-typeUnsigned widening add with 2*SEW results.
Instruction Syntax
vwaddu.wx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Related Search Terms
Instruction Behavior
VWADDU.WX extends inputs and adds them to produce 2*SEW-wide results. The W form adds a 2*SEW-wide vs2 source to an SEW-wide second operand.
VWADDU.WX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWADDU adds a zero-extended SEW second source to a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.
Instruction input
vwaddu.wx
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. The wide vd destination has EMUL=2 and must start at an even register; if it overlaps a SEW source, that source must be the highest-numbered register in the destination group. Such a legal different-EEW overlap is mask- and tail-agnostic regardless of vtype.vma/vta.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvwaddu.wx
funct6
110100
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffffffdf
0x00007fff
0x00010020
0x00001020
0xffffffdf
0x00007fff
0x00010020
0x00001020
w+
w+
w+
w+
w+
w+
w+
w+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwaddu.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWADDU.WX keeps add results in a wider destination, avoiding SEW-width wraparound from single-width add.
Destination elements are 2*SEW wide.
In W forms, vs2 is already wide and the second operand is extended from single width before addition.
Unsigned forms use zero extension.
Vector Execution Context
When reading VWADDU.WX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vwaddu.wx v8, v12, x5, v0.t».
Data Storing
Understand this scenario with real code like «vwaddu.wx v8, v12, x5, v0.t».
Vector Operations
Understand this scenario with real code like «vwaddu.wx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
In W forms, vs2 is already a 2*SEW-wide source.
The second operand is zero-extended before addition.
Destination elements remain 2*SEW wide.
FAQ
Is VWADDU.WX an accumulator instruction?
No. It produces widening add results; check VWADD.W* or dedicated multiply-accumulate/reduction instructions for accumulator semantics.