Is this an accumulator instruction?
No. It reads vs2 and rs1; equal-width vd/vs2 overlap is allowed.
VWADDU.WX
RISC-V VWADDU.WX Instruction Details
Instruction ManualV-typeAdd a zero-extended SEW scalar to wide vs2; keep low 2*SEW bits.
Instruction Syntax
vwaddu.wx vd, vs2, rs1, vm
Operand Breakdown
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 has EEW=2*SEW and EMUL=2*LMUL. rs1 is an integer scalar: take low SEW bits for XLEN>SEW or first sign-extend to SEW for XLEN<SEW, including unsigned addition; x0 supplies zero.
32-bit OP-V: opcode=1010111, funct6=110100, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. The syntax's final vm denotes optional v0.t; omission is unmasked.
For active elements, zero-extend the SEW second source to 2*SEW before adding to wide vs2; keep low 2*SEW result bits. No old-vd accumulation, saturation or vxsat change. Equal-width vd/vs2 may overlap. Group starts align to EMUL. Wide vd may overlap a narrow source only when source EMUL>=1 and their highest registers match; legal different-EEW overlap forces mask/tail agnostic.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. vm=0 uses v0.t; vm=1 is unmasked. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
VVector Operations
Instruction Behavior
V 1.0: convert rs1 to SEW bits by XLEN/SEW rules, zero-extend, then add to 2*SEW vs2 modulo 2^(2*SEW); old vd is not read.
VWADDU.WX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWADDU adds a zero-extended SEW second source to a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.
Instruction input
vwaddu.wx
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096 and vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer element support. Enter nonnegative bit patterns: 32-bit vs2 and 16-bit second source. Zero-extend the unsigned narrow source before addition; keep the low 32 result bits. Scalars first follow XLEN/SEW conversion: take low bits when XLEN>SEW and sign-extend when XLEN<SEW, including unsigned addition; x0 supplies zero. Wide vs2 has EMUL=2 and an even start; Equal-width vd/vs2 may overlap. With v0.t, vd and data sources exclude v0. Only body is shown, without definite inactive/tail values; Wide vd has EMUL=2 and an even start; a narrow source can overlap vd only at the destination group’s highest register, forcing agnostic behavior at different EEWs. VL=0 leaves vd unchanged; success resets vstart=0 and leaves vxsat unchanged. Stages are not processor cycles.
Execution Context
OP-V encodingvwaddu.wx
funct6
110100
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffffffdf
0x00007fff
0x00010020
0x00001020
0xffffffdf
0x00007fff
0x00010020
0x00001020
w+
w+
w+
w+
w+
w+
w+
w+
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwaddu.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening addition, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
Wide vs2 plus a narrow scalar, modulo 2^(2*SEW).
vd and vs2: EEW=2*SEW, EMUL=2*LMUL, at most 8.
Convert rs1 by XLEN/SEW rules, then zero-extend to 2*SEW; x0 supplies zero.
Vector Execution Context
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 has EEW=2*SEW and EMUL=2*LMUL. rs1 is an integer scalar: take low SEW bits for XLEN>SEW or first sign-extend to SEW for XLEN<SEW, including unsigned addition; x0 supplies zero.
32-bit OP-V: opcode=1010111, funct6=110100, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. The syntax's final vm denotes optional v0.t; omission is unmasked.
For active elements, zero-extend the SEW second source to 2*SEW before adding to wide vs2; keep low 2*SEW result bits. No old-vd accumulation, saturation or vxsat change. Equal-width vd/vs2 may overlap. Group starts align to EMUL. Wide vd may overlap a narrow source only when source EMUL>=1 and their highest registers match; legal different-EEW overlap forces mask/tail agnostic.
Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. vm=0 uses v0.t; vm=1 is unmasked. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
Common Usage Scenarios
Widening Add
Assume enabled V/VS, valid e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0, v0.mask[0..3]=1101; v12=[65535,32767,0,65535], x5=1. v8=[0x0000,0x8000,unchanged,0x0000], keeping low 16 bits. Lane2 and tails keep old values; vxsat is unchanged, and success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 has EEW=2*SEW and EMUL=2*LMUL. rs1 is an integer scalar: take low SEW bits for XLEN>SEW or first sign-extend to SEW for XLEN<SEW, including unsigned addition; x0 supplies zero.
- 32-bit OP-V: opcode=1010111, funct6=110100, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. The syntax's final vm denotes optional v0.t; omission is unmasked.
Semantic Check
- For active elements, zero-extend the SEW second source to 2*SEW before adding to wide vs2; keep low 2*SEW result bits. No old-vd accumulation, saturation or vxsat change. Equal-width vd/vs2 may overlap. Group starts align to EMUL. Wide vd may overlap a narrow source only when source EMUL>=1 and their highest registers match; legal different-EEW overlap forces mask/tail agnostic.
- Require RV32/RV64 V 1.0, enabled vector state, vill=0 and supported SEW/2*SEW. vm=0 uses v0.t; vm=1 is unmasked. Only mask-enabled vstart<=i<vl elements compute; prestart stays unchanged and inactive/tail follow vma/vta. Masked vd excludes v0, which cannot supply both EEW=1 mask and data. vstart>=vl (including vl=0) leaves every destination element unchanged; success resets vstart=0.
Pitfalls / Common Confusions
The .w form reads vs2 at 2*SEW bits.
Zero-extend the SEW scalar before addition.
The destination remains 2*SEW bits wide.