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VWADDU.WV

RISC-V VWADDU.WV Instruction Details

Instruction ManualR-type

Unsigned widening add with 2*SEW results.

Instruction Syntax

vwaddu.wv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Related Search Terms
VWADDU.WV instructionvwaddu.wv syntaxwidening addRVV wideningunsigned widening

Instruction Behavior

VWADDU.WV extends inputs and adds them to produce 2*SEW-wide results. The W form adds a 2*SEW-wide vs2 source to an SEW-wide second operand.

Quick Understanding & Search Notes

VWADDU.WV keeps add results in a wider destination, avoiding SEW-width wraparound from single-width add.

Destination elements are 2*SEW wide.
In W forms, vs2 is already wide and the second operand is extended from single width before addition.
Unsigned forms use zero extension.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VWADDU.WV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vwaddu.wv v8, v12, v4, v0.t».

Data Storing

Understand this scenario with real code like «vwaddu.wv v8, v12, v4, v0.t».

Vector Operations

Understand this scenario with real code like «vwaddu.wv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In W forms, vs2 is already a 2*SEW-wide source.
The second operand is zero-extended before addition.
Destination elements remain 2*SEW wide.

FAQ

Is VWADDU.WV an accumulator instruction?

No. It produces widening add results; check VWADD.W* or dedicated multiply-accumulate/reduction instructions for accumulator semantics.