What determines the element count for vwredsum.vs?
The current vl and optional v0.t mask select participating vs2 elements; vstart must be zero. For vl>0 the seed participates even with an all-zero mask; vl=0 leaves the destination unchanged.
VWREDSUM.VS
RISC-V VWREDSUM.VS Instruction Details
Instruction ManualOPIVVVWREDSUM.VS uses the vs1[0] seed to perform signed widening sum reduction over active vs2 elements, writing only vd[0].
Instruction Syntax
vwredsum.vs vd, vs2, vs1, vm
Operand Breakdown
vd[0] and vs1[0] are 2*SEW scalars in single vector registers with EMUL=1, not wide register groups; vs2 is a SEW/LMUL vector source.
32-bit OP-V: opcode=1010111, funct6=110001, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Sign-extend active vs2 elements to 2*SEW, add vs1[0], and wrap at 2*SEW. Only vd[0] receives the result; other destination elements are tails. With vl>0 an all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources or v0. vs2 and vs1 cannot read one register at different EEWs; v0 cannot provide both EEW=1 mask and data. Tails normally follow vta, preserving old values or permitting all ones; legal different-EEW source/destination overlap forces tail-agnostic behavior.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector Operations
Instruction Behavior
VWREDSUM.VS is a RISC-V V extension signed widening integer reduction instruction. Syntax is `vwredsum.vs vd, vs2, vs1, vm`; it uses vs1[0] as the seed, includes only masked-in active vs2 elements within the current vl in the signed widening sum reduction, and writes the final 2*SEW-wide result to vd[0]. Active vs2 elements are widened as signed values before accumulation with the 2*SEW seed. With vl=0, no reduction runs and no destination element is updated. With vl>0 and every vs2 element masked off, vs1[0] is still written to vd[0]. Sum overflow wraps at 2*SEW bits without saturation.
VWREDSUM.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWREDSUM uses vs1[0] as the seed, reduces only active vs2 elements, and writes the 2*SEW-wide widening result to vd[0].
Instruction input
vwredsum.vs
Teaching context: V 1.0, enabled vector state, valid supported vtype, LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative bit patterns; sign-extend signed SEW vs2 values and add the 2*SEW seed, wrapping at 2*SEW without saturation or vxsat change. vs1[0] and vd[0] are wide scalars in single registers with EMUL=1; any v0-v31 may be vd, overlapping sources or the mask. vs2 and vs1 cannot read the same register at different EEWs; v0 cannot supply mask and data together. With VL>0, an all-zero mask still writes the seed; VL=0 updates nothing. Other destination elements are tails normally governed by vta; legal different-EEW source/destination overlap forces tail-agnostic behavior. No definite tail values are displayed. Nonzero vstart raises an illegal-instruction exception; stages are not processor cycles.
Execution Context
OP-V encodingvwredsum.vs
funct6
110001
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x00000003
0x00000007
0x00000007
0x00000018
0x00000008
0x0000000f
0x0000000f
0x00000013
v8
0x0004
0xfffd
0x0011
0xfff0
0x0007
0x0020
0x0004
0xfffd
acc+
acc+
acc+
acc+
acc+
acc+
acc+
acc+
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vwredsum.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, vs1[0]-seeded reduction integer signed widening sum reduction, mask participation filtering, and vd[0] writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vwredsum.vs is a V extension vector instruction. Participating vs2 elements are selected by the current vl and optional v0.t mask; vstart must be 0. Active vs2 elements are widened and reduced with the 2*SEW-wide seed in vs1[0], with the result only in vd[0].
Official syntax is `vwredsum.vs vd, vs2, vs1, vm`; without a mask operand it is unmasked, while with `, v0.t` masked-off vs2 elements do not participate in the reduction.
vs1[0] is the 2*SEW-wide reduction seed; active vs2 elements are widened before participating in the sum reduction.
Reduction instructions require vstart=0; do not treat them as element-wise additions restartable from an arbitrary element.
The reduction result is written only to vd[0]; the other elements in that destination register are tails normally managed by vtype.vta; legal different-EEW source/destination overlap forces tail-agnostic behavior.
Requires enabled vector state, valid vtype and support for SEW and 2*SEW; widening SEW=64 needs additional 128-bit integer element support.
With vl=0, no reduction runs and no destination element is updated. With vl>0 and every vs2 element masked off, vs1[0] is still written to vd[0]. Sum overflow wraps at 2*SEW bits without saturation.
vs1[0] and vd[0] are 2*SEW scalars in single vector registers with EMUL=1. The destination may overlap sources or the mask, but a source register cannot be read at different EEWs.
Vector Execution Context
vd[0] and vs1[0] are 2*SEW scalars in single vector registers with EMUL=1, not wide register groups; vs2 is a SEW/LMUL vector source.
32-bit OP-V: opcode=1010111, funct6=110001, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Sign-extend active vs2 elements to 2*SEW, add vs1[0], and wrap at 2*SEW. Only vd[0] receives the result; other destination elements are tails. With vl>0 an all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources or v0. vs2 and vs1 cannot read one register at different EEWs; v0 cannot provide both EEW=1 mask and data. Tails normally follow vta, preserving old values or permitting all ones; legal different-EEW source/destination overlap forces tail-agnostic behavior.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Signed widening sum reduction
Assume enabled V/VS, valid supported e16,m1,tu,mu, supported 32-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v12=[65535,2,32768,4], v0.mask[0..3]=1111. vs1[0]=10; 10 + (-1) + 2 + (-32768) + 4 = -32753 → vd[0]=0xffff800f. Tails retain old values; success resets vstart=0.
V standard vector extension
Assume enabled V/VS, valid supported e16,m1,tu,mu, supported 32-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v12=[65535,2,32768,4], v0.mask[0..3]=1111. vs1[0]=10; 10 + (-1) + 2 + (-32768) + 4 = -32753 → vd[0]=0xffff800f. Tails retain old values; success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd[0] and vs1[0] are 2*SEW scalars in single vector registers with EMUL=1, not wide register groups; vs2 is a SEW/LMUL vector source.
- 32-bit OP-V: opcode=1010111, funct6=110001, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Syntax source order: vs2, vs1. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Sign-extend active vs2 elements to 2*SEW, add vs1[0], and wrap at 2*SEW. Only vd[0] receives the result; other destination elements are tails. With vl>0 an all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
- vd may overlap sources or v0. vs2 and vs1 cannot read one register at different EEWs; v0 cannot provide both EEW=1 mask and data. Tails normally follow vta, preserving old values or permitting all ones; legal different-EEW source/destination overlap forces tail-agnostic behavior.
- RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. Success resets vstart=0 without saturation or vxsat change. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.
FAQ
Does vwredsum.vs always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.