Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWREDSUMU.VS
RISC-V VWREDSUMU.VS Instruction Details
Instruction ManualR-typeVWREDSUMU.VS uses the vs1[0] seed to perform unsigned widening sum reduction over active vs2 elements, writing only vd[0].
Instruction Syntax
vwredsumu.vs vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
VWREDSUMU.VS is a RISC-V V extension unsigned widening integer reduction instruction. Syntax is `vwredsumu.vs vd, vs2, vs1, vm`; it uses vs1[0] as the seed, includes only masked-in active vs2 elements within the current vl in the unsigned widening sum reduction, and writes the final 2*SEW-wide result to vd[0]. Active vs2 elements are widened as unsigned values before accumulation with the 2*SEW seed.
VWREDSUMU.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWREDSUMU uses vs1[0] as the seed, reduces only active vs2 elements, and writes the 2*SEW-wide widening result to vd[0].
Instruction input
vwredsumu.vs
OP-V encodingvwredsumu.vs
funct6
110000
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x00000003
0x00000007
0x00000007
0x00000018
0x0000001a
0x00000021
0x00000021
0x00000025
v8
0x0004
0x0009
0x0011
0x0002
0x0007
0x0020
0x0004
0x0009
acc+
acc+
acc+
acc+
acc+
acc+
acc+
acc+
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vwredsumu.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, vs1[0]-seeded reduction integer unsigned widening sum reduction, mask participation filtering, and vd[0] writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vwredsumu.vs is a V extension vector instruction. Participating vs2 elements are selected by the current vl and optional v0.t mask; vstart must be 0. Active vs2 elements are widened and reduced with the 2*SEW-wide seed in vs1[0], with the result only in vd[0].
Official syntax is `vwredsumu.vs vd, vs2, vs1, vm`; without a mask operand it is unmasked, while with `, v0.t` masked-off vs2 elements do not participate in the reduction.
vs1[0] is the 2*SEW-wide reduction seed; active vs2 elements are widened before participating in the sum reduction.
Reduction instructions require vstart=0; do not treat them as element-wise additions restartable from an arbitrary element.
The reduction result is written only to vd[0]; elements other than vd[0] do not have the same result meaning.
Vector Execution Context
When reading VWREDSUMU.VS, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Unsigned widening sum
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Vector reduction
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Statistical aggregation
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1[0] is the reduction seed; do not treat the whole vs1 register as a second element-wise source.
Only vd[0] holds the reduction result; other destination elements are not per-lane outputs.
vs2 elements masked off by v0.t do not participate, while the vs1[0] seed remains the starting value.
A reduction is not an ordinary element-wise ALU instruction; do not interpret the result as being broadcast to every element.
Do not treat integer reduction as an element-wise operation restartable from an arbitrary vstart; the official requirement is vstart=0.
FAQ
What determines the element count for vwredsumu.vs?
The current vl and optional v0.t mask determine which vs2 elements participate; this integer reduction class requires vstart=0, and the vs1[0] seed always participates.
Does vwredsumu.vs always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.