What determines the element count for vwredsumu.vs?
The current vl and vtype determine it, with vstart, LMUL, SEW, mask state, and tail policy also affecting execution.
VWREDSUMU.VS
RISC-V VWREDSUMU.VS Instruction Details
Instruction ManualR-typeVWREDSUMU.VS performs an unsigned widening sum reduction and writes the result to vd[0].
Instruction Syntax
vwredsumu.vs vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Instruction Behavior
vwredsumu.vs widens active vs2 elements as unsigned values, reduces them with the scalar seed in vs1[0], and writes the reduction result to vd[0].
Quick Understanding & Search Notes
vwredsumu.vs is a V extension vector instruction. Active elements are controlled by vl, vtype, vstart, and the optional v0.t mask; active vs2 elements are widened and reduced with the seed in vs1[0], with the result only in vd[0].
Official syntax is `vwredsumu.vs vd, vs2, vs1, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply zeroing.
A reduction is not element-wise addition; elements other than vd[0] do not have the same result meaning.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Data Storing
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Vector Operations
Understand this scenario with real code like «vwredsumu.vs v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only vd[0] holds the reduction result; do not interpret the whole vd group as element-wise output.
Integer sum reduction follows V reduction rules; software must not depend on a particular intermediate tree order.
Masked-off elements do not participate, and tail elements follow policy.
FAQ
Does vwredsumu.vs always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.