How does an all-zero mask differ from vl=0?
With vl>0 and all source elements masked off, vd[0] still receives the vs1[0] seed. With vl=0, the destination is entirely unchanged and the seed is not copied.
VWREDSUMU.VS
RISC-V VWREDSUMU.VS Instruction Details
Instruction ManualV-typeVWREDSUMU.VS zero-extends active SEW elements and sums them with a 2*SEW seed; when vl>0, the result is written to vd[0].
Instruction Syntax
vwredsumu.vs vd, vs2, vs1, vm
Operand Breakdown
vs2 is a SEW/LMUL vector source. The 2*SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register, with EMUL=1.
32-bit OP-V: opcode=1010111, funct6=110000, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend active vs2 elements, add the wide seed and wrap at 2*SEW. With vl>0, only vd[0] holds the result and other elements are tails. An all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources or v0. vs2 and vs1 cannot read one register with different EEWs; v0 cannot supply both EEW=1 mask and data. Other destination elements normally follow vta; legal different-EEW source/destination overlap forces tail-agnostic behavior.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector Operations
Instruction Behavior
VWREDSUMU.VS is a V 1.0 unsigned widening sum reduction. vs2 elements are SEW wide; the vs1[0] seed and vd[0] result are 2*SEW wide. Active source elements are zero-extended before summation, with overflow wrapping at 2*SEW. With vl>0, an all-zero mask still writes the seed; vl=0 leaves the destination unchanged. Nonzero vstart raises an illegal-instruction exception.
VWREDSUMU.VS Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWREDSUMU uses vs1[0] as the seed, reduces only active vs2 elements, and writes the 2*SEW-wide widening result to vd[0].
Instruction input
vwredsumu.vs
Teaching context: V 1.0, enabled vector state, valid supported vtype, LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative bit patterns; zero-extend unsigned SEW vs2 values and add the 2*SEW seed, wrapping at 2*SEW without saturation or vxsat change. vs1[0] and vd[0] are wide scalars in single registers with EMUL=1; any v0-v31 may be vd, overlapping sources or the mask. vs2 and vs1 cannot read the same register at different EEWs; v0 cannot supply mask and data together. With VL>0, an all-zero mask still writes the seed; VL=0 updates nothing. Other destination elements are tails normally governed by vta; legal different-EEW source/destination overlap forces tail-agnostic behavior. No definite tail values are displayed. Nonzero vstart raises an illegal-instruction exception; stages are not processor cycles.
Execution Context
OP-V encodingvwredsumu.vs
funct6
110000
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
acc
0x00000003
0x00000007
0x00000007
0x00000018
0x0000001a
0x00000021
0x00000021
0x00000025
v8
0x0004
0x0009
0x0011
0x0002
0x0007
0x0020
0x0004
0x0009
acc+
acc+
acc+
acc+
acc+
acc+
acc+
acc+
v0.t
1
0
1
1
1
0
1
1
v4
...
tail
tail
tail
tail
tail
tail
tail
Current step
Show OP-V 32-bit encoding fields
vwredsumu.vs uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, vs1[0]-seeded reduction integer unsigned widening sum reduction, mask participation filtering, and vd[0] writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWREDSUMU.VS zero-extends active SEW elements and sums them with a 2*SEW seed; when vl>0, the result is written to vd[0].
Syntax is `vwredsumu.vs vd, vs2, vs1, vm`; omitting the mask means vm=1, while v0.t means vm=0 and only masked-in vs2 elements participate.
Compute vd[0] = (vs1[0] + sum(zext(vs2[i]))) mod 2^(2*SEW), over active i only; SEW and 2*SEW must be supported.
vs1[0] and vd[0] are wide scalars in single vector registers with EMUL=1; vd may overlap sources or v0. A register cannot be read as sources at different EEWs, including EEW=1 mask data.
With vl>0, only vd[0] holds the reduction result; other destination elements are tails governed by vta. Legal different-EEW source/destination overlap forces agnostic behavior. vl=0 updates no destination elements.
vstart must be zero, otherwise an illegal-instruction exception is raised. Encoding is OP-V=1010111, funct3=000 (OPIVV), funct6=110000.
Vector Execution Context
vs2 is a SEW/LMUL vector source. The 2*SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register, with EMUL=1.
32-bit OP-V: opcode=1010111, funct6=110000, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend active vs2 elements, add the wide seed and wrap at 2*SEW. With vl>0, only vd[0] holds the result and other elements are tails. An all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
vd may overlap sources or v0. vs2 and vs1 cannot read one register with different EEWs; v0 cannot supply both EEW=1 mask and data. Other destination elements normally follow vta; legal different-EEW source/destination overlap forces tail-agnostic behavior.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Unsigned widening sum
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[255,1,0,0], v4[0]=65535 → v8[0]=255 (0x00ff). Other destination elements are tails and retain old values. Success resets vstart=0.
Vector reduction
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[255,1,0,0], v4[0]=65535 → v8[0]=255 (0x00ff). Other destination elements are tails and retain old values. Success resets vstart=0.
Statistical aggregation
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[255,1,0,0], v4[0]=65535 → v8[0]=255 (0x00ff). Other destination elements are tails and retain old values. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vs2 is a SEW/LMUL vector source. The 2*SEW seed vs1[0] and result vd[0] each occupy element 0 of any single vector register, with EMUL=1.
- 32-bit OP-V: opcode=1010111, funct6=110000, funct3=000 (OPIVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Zero-extend active vs2 elements, add the wide seed and wrap at 2*SEW. With vl>0, only vd[0] holds the result and other elements are tails. An all-zero mask still writes the seed; vl=0 updates nothing. Nonzero vstart raises an illegal-instruction exception.
- vd may overlap sources or v0. vs2 and vs1 cannot read one register with different EEWs; v0 cannot supply both EEW=1 mask and data. Other destination elements normally follow vta; legal different-EEW source/destination overlap forces tail-agnostic behavior.
- RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
vl=0 does not copy the seed; an all-zero mask with vl>0 still writes the seed.
Only vd[0] holds the result; other destination elements follow the tail policy.
Nonzero vstart raises an illegal-instruction exception; wide scalars use EMUL=1, unlike ordinary widening destination groups.
FAQ
How does an example with SEW=8 work?
Assume a supported configuration, vstart=0, vl=2, unmasked, vs2=[255,1], and a 16-bit seed of 65535. (65535+255+1) mod 65536 = 255, so vd[0]=0x00ff. Other destination elements are tails.