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VWSUB.WV

RISC-V VWSUB.WV Instruction Details

Instruction ManualR-type

VWSUB.WV performs signed widening subtraction.

Instruction Syntax

vwsub.wv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Related Search Terms
vwsub.wv instructionvwsub wvvwsub.wv RVVvwsub.wv vl vtypesigned widening subtractionvwsub.wv mask

Instruction Behavior

vwsub.wv is a V extension signed widening subtraction instruction. The first source vs2 is already 2*SEW wide; the other SEW source is widened before subtraction. The result is written to 2*SEW-wide vd.

Quick Understanding & Search Notes

vwsub.wv is a V extension vector instruction. Active elements are controlled by vl, vtype, vstart, and the optional v0.t mask; it subtracts a widened source operand from 2*SEW-wide vs2.

Official syntax is `vwsub.wv vd, vs2, vs1, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply zeroing.
The .w suffix means a wide source participates; this is not ordinary narrow vector subtraction.
RISC-V Unprivileged ISA Manual, V standard vector extension

Vector Execution Context

When reading VWSUB.WV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vwsub.wv v8, v12, v4, v0.t».

Data Storing

Understand this scenario with real code like «vwsub.wv v8, v12, v4, v0.t».

Vector Operations

Understand this scenario with real code like «vwsub.wv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In .w forms, vs2 is the wide source operand; do not read it as two narrow sources.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.

FAQ

What determines the element count for vwsub.wv?

The current vl and vtype determine it, with vstart, LMUL, SEW, mask state, and tail policy also affecting execution.

Does vwsub.wv always process the whole vector register?

No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.