Does VWSUB.WX accumulate old vd?
No. .vv/.vx read two narrow sources; .wv/.wx read wide vs2 and a narrow second source. Both subtract the second source from vs2 and write vd.
VWSUB.WX
RISC-V VWSUB.WX Instruction Details
Instruction ManualV-typeVWSUB.WX subtracts a sign-extended SEW second source from 2*SEW vs2, writing a 2*SEW result.
Instruction Syntax
vwsub.wx vd, vs2, rs1, vm
Operand Breakdown
vd has EEW=2*SEW, EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is rs1 converted to SEW. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110111, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Sign-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 supplies zero. Active elements satisfy vstart<=i<vl with mask enabled. vstart>=vl (including vl=0) updates nothing; implementations may reject nonzero vstart values they cannot produce.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers; legal different-EEW source/destination overlap forces mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or becoming all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector Operations
Instruction Behavior
vwsub.wx is a V 1.0 signed widening subtraction instruction. vs2 is already 2*SEW wide; the sign-extended rs1 is subtracted from vs2 and the low 2*SEW result bits are written to vd. rs1 first follows XLEN/SEW conversion: take low SEW bits when XLEN>SEW, or sign-extend to SEW when XLEN<SEW.
VWSUB.WX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSUB subtracts a sign-extended SEW second source from a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.
Instruction input
vwsub.wx
Teaching context: V 1.0, enabled vector state, valid supported vtype; LMUL=m1, VLEN=4096, vstart=0. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements. Enter nonnegative bit patterns: 32-bit vs2 and 16-bit second source, interpreted as signed two’s-complement. Sign-extend narrow sources before subtracting the second source from vs2, keeping low 32 bits without saturation, vxrm use or vxsat change. Scalars first follow XLEN/SEW conversion: take low bits if wider, sign-extend if narrower; x0 supplies zero. Wide vs2 has EMUL=2 and an even start; equal-width vd/vs2 may overlap. Wide vd has EMUL=2 and an even start; a narrow source may overlap only its highest register, forcing mask/tail-agnostic behavior. With v0.t, vd and data sources exclude v0. Only body is shown without definite inactive/tail values. VL=0 updates nothing; success resets vstart=0. Stages are not processor cycles.
Execution Context
OP-V encodingvwsub.wx
funct6
110111
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x80000020
0x00007fff
0xffffffee
0x00001020
0x80000020
0x00007fff
0xffffffee
0x00001020
w-
w-
w-
w-
w-
w-
w-
w-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsub.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer signed widening subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWSUB.WX subtracts a sign-extended SEW second source from 2*SEW vs2, writing a 2*SEW result.
Syntax is `vwsub.wx vd, vs2, rs1, vm`; vm=1 is unmasked, vm=0 uses v0.t. Active elements depend on vl, vstart and the mask; vl=0 updates no destination elements.
vs2 is already 2*SEW wide; sign-extend the second source to 2*SEW and subtract it from vs2. rs1 first takes low SEW bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 supplies zero.
Require supported SEW and 2*SEW. Destination EEW=2*SEW, EMUL=2*LMUL, with no group larger than 8 registers. Wide groups start at even registers for LMUL=m1. Wide vs2 may overlap equal-width vd.
A narrow source may overlap only the highest part of a wider destination group, with source EMUL at least 1; legal different-EEW source/destination overlap forces mask/tail-agnostic behavior. With v0.t, destination and data sources exclude v0.
Results wrap at 2*SEW without accumulating old vd, using vxrm or changing vxsat. Inactive/tail elements follow vma/vta, without guaranteed zeroing. Encoding is OP-V=1010111, funct3=110, funct6=110111.
Vector Execution Context
vd has EEW=2*SEW, EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is rs1 converted to SEW. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110111, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Sign-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 supplies zero. Active elements satisfy vstart<=i<vl with mask enabled. vstart>=vl (including vl=0) updates nothing; implementations may reject nonzero vstart values they cannot produce.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers; legal different-EEW source/destination overlap forces mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or becoming all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Vector Integer Arithmetic
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[65520,0,0,0], x5=255 → vd[0]=0xfff1 (-15). Other body results are 1 and tails retain old values. Success resets vstart=0.
Signed Widening Subtraction
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[65520,0,0,0], x5=255 → vd[0]=0xfff1 (-15). Other body results are 1 and tails retain old values. Success resets vstart=0.
Vectorized Loops
Assume enabled V/VS, valid supported e8,m1,tu,mu, supported 16-bit results, VLEN=4096, XLEN=64, vl=4, vstart=0; v0.mask[0..3]=1111. v12=[65520,0,0,0], x5=255 → vd[0]=0xfff1 (-15). Other body results are 1 and tails retain old values. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd has EEW=2*SEW, EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is rs1 converted to SEW. Wide groups align to their size.
- 32-bit OP-V: opcode=1010111, funct6=110111, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Sign-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW; x0 supplies zero. Active elements satisfy vstart<=i<vl with mask enabled. vstart>=vl (including vl=0) updates nothing; implementations may reject nonzero vstart values they cannot produce.
- Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers; legal different-EEW source/destination overlap forces mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or becoming all ones, without guaranteed zeroing.
- RV32/RV64 V 1.0; require enabled vector state, vill=0, supported SEW and 2*SEW. SEW=64 needs additional 128-bit integer elements. No saturation, vxrm use or vxsat change; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
In .w forms, vs2 is the wide source operand; do not read it as two narrow sources.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.
FAQ
How are negative values interpreted with SEW=8?
Assume a supported configuration, vstart=0, vl=1, unmasked. 16-bit vs2=0xfff0 represents -16 and the second source 0xff represents -1, giving -16-(-1)=-15, encoded as 16-bit 0xfff1.