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CSR Bit Fields

RISC-V dcsr CSR Register

Address 0x7B0Privilege Debug mode onlyAccess RW / 32Debug, trace, and trigger CSRs

dcsr at 0x7B0 is the Debug Control and Status CSR, visible only in Debug mode.

Bit Overview

Hover for details · Click to jump↗Open Official Manual

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32prv1:0WARL

Reserved63:32debugver31:28ROstep2RW prv1:0WARL

Field Map

Understand dcsr By Bit Fields

19 key fields

31:28

debugver

Debug specification version encoding.

debugver (bits 31:28) — Debug specification version encoding.

What This Field Controls

- Debug specification version encoding.

Common Values

dcsr.debugver

0No debug support

There is no external debug support.

1-3Reserved

The RISC-V Debug Specification 1.0 does not define current portable meanings for these encodings.

4Debug 1.0

Debug support exists as described by the RISC-V Debug Specification 1.0.

5-14Reserved

Reserved encodings; portable software must not write or depend on them.

15Custom

Debug support exists, but it does not conform to any available version of the RISC-V Debug Specification.

↗Open Official Manual

ebreakm

Enter Debug Mode on EBREAK in M-mode.

ebreakm (bit 15) — Enter Debug Mode on EBREAK in M-mode.

What This Field Controls

- Enter Debug Mode on EBREAK in M-mode.

Common Values

dcsr.ebreakm

0Exception path

An EBREAK executed in M-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in M-mode enters Debug Mode.

↗Open Official Manual

ebreaks

WARL

Controls whether S-mode EBREAK enters Debug Mode; hardwired to zero without S-mode support.

ebreaks (bit 13) — Controls whether S-mode EBREAK enters Debug Mode; hardwired to zero without S-mode support.

What This Field Controls

- Controls whether S-mode EBREAK enters Debug Mode; hardwired to zero without S-mode support.

Common Values

dcsr.ebreaks

0Exception path

An EBREAK executed in S-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in S-mode enters Debug Mode.

↗Open Official Manual

ebreaku

WARL

Controls whether U-mode EBREAK enters Debug Mode; hardwired to zero without U-mode support.

ebreaku (bit 12) — Controls whether U-mode EBREAK enters Debug Mode; hardwired to zero without U-mode support.

What This Field Controls

- Controls whether U-mode EBREAK enters Debug Mode; hardwired to zero without U-mode support.

Common Values

dcsr.ebreaku

0Exception path

An EBREAK executed in U-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in U-mode enters Debug Mode.

↗Open Official Manual

stepie

WARL

Whether interrupts, including NMI, are enabled during single-step; an implementation may hardwire it to zero, and a debugger must not change it while the hart runs.

stepie (bit 11) — Whether interrupts, including NMI, are enabled during single-step; an implementation may hardwire it to zero, and a debugger must not change it while the hart runs.

What This Field Controls

- Whether interrupts, including NMI, are enabled during single-step; an implementation may hardwire it to zero, and a debugger must not change it while the hart runs.

Common Values

dcsr.stepie

0Interrupts disabled during step

Interrupts are disabled during single-step execution.

1Interrupts enabled during step

Interrupts are enabled during single-step execution.

↗Open Official Manual

stopcount

WARL

Controls whether hart-local counters freeze in Debug Mode; an implementation may hardwire it to zero or one.

stopcount (bit 10) — Controls whether hart-local counters freeze in Debug Mode; an implementation may hardwire it to zero or one.

What This Field Controls

- Controls whether hart-local counters freeze in Debug Mode; an implementation may hardwire it to zero or one.

Common Values

dcsr.stopcount

0Counters continue

Hart-local counters increment as usual in Debug Mode.

1Counters frozen

Hart-local counters do not increment while in Debug Mode or on EBREAK instructions that cause entry into Debug Mode.

↗Open Official Manual

stoptime

WARL

Controls whether time freezes in Debug Mode; an implementation may hardwire it to zero or one.

stoptime (bit 9) — Controls whether time freezes in Debug Mode; an implementation may hardwire it to zero or one.

What This Field Controls

- Controls whether time freezes in Debug Mode; an implementation may hardwire it to zero or one.

Common Values

dcsr.stoptime

0Timers continue

time continues to reflect mtime.

1Timers frozen

time freezes on Debug Mode entry and reflects the latest mtime again on exit; mtime may stop incrementing while all harts have this value and are in Debug Mode.

↗Open Official Manual

8:6

cause

Cause code for entering Debug Mode.

cause (bits 8:6) — Cause code for entering Debug Mode.

What This Field Controls

- Cause code for entering Debug Mode.

Common Values

dcsr.cause

0Reserved

Reserved encoding; portable software must not depend on its meaning.

1EBREAK

Debug Mode was entered because of an EBREAK instruction.

2Trigger

Debug Mode was entered because of the trigger module.

3Halt request

Debug Mode was entered because of a debugger halt request.

4Step

Debug Mode was entered because of single-step execution.

5Reset halt request

Debug Mode was entered directly out of reset because of a reset halt request.

6Halt group

Debug Mode was entered because of a halt group request.

7Other / extended cause

Debug Mode was entered for another reason; if extcause is implemented, extcause may provide a more specific reason.

↗Open Official Manual

step

Single-step execution control.

step (bit 2) — Single-step execution control.

What This Field Controls

- Single-step execution control.

Common Values

dcsr.step

0No single step

No single-step execution is requested after resume.

1Single step

After resume, the hart executes one instruction and re-enters Debug Mode.

↗Open Official Manual

1:0

prv

WARL

Records the privilege mode before Debug Mode entry and can control the resume privilege mode; if a written mode is unsupported or cannot be selected, the hart may change to any supported mode.

prv (bits 1:0) — Records the privilege mode before Debug Mode entry and can control the resume privilege mode; if a written mode is unsupported or cannot be selected, the hart may change to any supported mode.

What This Field Controls

- Records the privilege mode before Debug Mode entry and can control the resume privilege mode; if a written mode is unsupported or cannot be selected, the hart may change to any supported mode.

Common Values

dcsr.prv

0User

Resume execution at User privilege level.

1Supervisor

Resume execution at Supervisor privilege level.

2Reserved

Reserved privilege-level encoding; portable software must not write or depend on it.

3Machine

Resume execution at Machine privilege level.

↗Open Official Manual

27, 23:20, 14

Reserved

RO zero

Reserved bits that read as zero.

Reserved (bits 27, 23:20, 14) — Reserved bits that read as zero.

What This Field Controls

- Reserved bits that read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

26:24

extcause

Only when cause is 7, optionally gives a more specific halt reason; otherwise it is zero. The currently defined value 0 denotes an Smdbltrp critical error.

extcause (bits 26:24) — Only when cause is 7, optionally gives a more specific halt reason; otherwise it is zero. The currently defined value 0 denotes an Smdbltrp critical error.

What This Field Controls

- Only when cause is 7, optionally gives a more specific halt reason; otherwise it is zero. The currently defined value 0 denotes an Smdbltrp critical error.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

cetrig

WARL (Smdbltrp only)

Smdbltrp critical-error Debug Mode entry control; absent when that extension is not implemented.

cetrig (bit 19) — Smdbltrp critical-error Debug Mode entry control; absent when that extension is not implemented.

What This Field Controls

- Smdbltrp critical-error Debug Mode entry control; absent when that extension is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

pelp

WARL (Zicfilp only)

Zicfilp previous ELP state; absent when Zicfilp is not implemented.

pelp (bit 18) — Zicfilp previous ELP state; absent when Zicfilp is not implemented.

What This Field Controls

- Zicfilp previous ELP state; absent when Zicfilp is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

ebreakvs

WARL

Controls whether VS-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

ebreakvs (bit 17) — Controls whether VS-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

What This Field Controls

- Controls whether VS-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

ebreakvu

WARL

Controls whether VU-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

ebreakvu (bit 16) — Controls whether VU-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

What This Field Controls

- Controls whether VU-mode EBREAK enters Debug Mode; hardwired zero without virtualization mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

v

WARL

Virtualization mode before Debug Mode entry and for resume; hardwired zero without virtualization mode.

v (bit 5) — Virtualization mode before Debug Mode entry and for resume; hardwired zero without virtualization mode.

What This Field Controls

- Virtualization mode before Debug Mode entry and for resume; hardwired zero without virtualization mode.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

mprven

WARL

Controls whether mstatus.MPRV takes effect in Debug Mode; this optional bit may be tied to 0 or 1.

mprven (bit 4) — Controls whether mstatus.MPRV takes effect in Debug Mode; this optional bit may be tied to 0 or 1.

What This Field Controls

- Controls whether mstatus.MPRV takes effect in Debug Mode; this optional bit may be tied to 0 or 1.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

nmip

NMI-pending indication; reliable debugging may no longer be possible when set, depending on the implementation.

nmip (bit 3) — NMI-pending indication; reliable debugging may no longer be possible when set, depending on the implementation.

What This Field Controls

- NMI-pending indication; reliable debugging may no longer be possible when set, depending on the implementation.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

- First confirm that the current hart and debug implementation provide dcsr.
- dcsr is in the 0x7B0-0x7BF Debug-mode-only CSR range; ordinary M-mode software must not treat it as a directly accessible Machine CSR.
- Access it only in Debug mode or in a context defined by the Debug Specification, and interpret fields according to the debug spec and implementation.

Risk Checks Before Writing

- Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
- Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

After entering Debug mode, read dcsr according to the Debug Specification.

Modify only target debug fields and preserve unchanged or implementation-defined fields.

Validate the setting through resume, single-step, or debug-module behavior.