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CSR Bit Fields

RISC-V dcsr CSR Register

Address 0x7B0Privilege Debug mode onlyAccess RW / XLENDebug, trace, and trigger CSRs

dcsr at 0x7B0 is the Debug Control and Status CSR, visible only in Debug mode.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32prv1:0RW
Field Map

Understand dcsr By Bit Fields

10 key fields
31:28

xdebugver

RO

External debug specification version encoding.

xdebugver (bits 31:28) — External debug specification version encoding.

What This Field Controls

  • - External debug specification version encoding.

Common Values

dcsr.xdebugver
0No debug support

There is no external debug support.

1-3Reserved

The RISC-V Debug Specification 1.0 does not define current portable meanings for these encodings.

4Debug 1.0

Debug support exists as described by the RISC-V Debug Specification 1.0.

5-14Reserved

Reserved encodings; portable software must not write or depend on them.

15Custom

Debug support exists, but it does not conform to any available version of the RISC-V Debug Specification.

↗Open Official Manual
15

ebreakm

RW

Enter Debug Mode on EBREAK in M-mode.

ebreakm (bit 15) — Enter Debug Mode on EBREAK in M-mode.

What This Field Controls

  • - Enter Debug Mode on EBREAK in M-mode.

Common Values

dcsr.ebreakm
0Exception path

An EBREAK executed in M-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in M-mode enters Debug Mode.

↗Open Official Manual
13

ebreaks

RW

Enter Debug Mode on EBREAK in S-mode.

ebreaks (bit 13) — Enter Debug Mode on EBREAK in S-mode.

What This Field Controls

  • - Enter Debug Mode on EBREAK in S-mode.

Common Values

dcsr.ebreaks
0Exception path

An EBREAK executed in S-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in S-mode enters Debug Mode.

↗Open Official Manual
12

ebreaku

RW

Enter Debug Mode on EBREAK in U-mode.

ebreaku (bit 12) — Enter Debug Mode on EBREAK in U-mode.

What This Field Controls

  • - Enter Debug Mode on EBREAK in U-mode.

Common Values

dcsr.ebreaku
0Exception path

An EBREAK executed in U-mode follows the breakpoint-exception behavior defined by the privileged architecture.

1Enter Debug Mode

An EBREAK executed in U-mode enters Debug Mode.

↗Open Official Manual
11

stepie

RW

Whether interrupts are enabled during single-step.

stepie (bit 11) — Whether interrupts are enabled during single-step.

What This Field Controls

  • - Whether interrupts are enabled during single-step.

Common Values

dcsr.stepie
0Interrupts disabled during step

Interrupts are disabled during single-step execution.

1Interrupts enabled during step

Interrupts are enabled during single-step execution.

↗Open Official Manual
10

stopcount

RW

Whether counters stop in Debug Mode.

stopcount (bit 10) — Whether counters stop in Debug Mode.

What This Field Controls

  • - Whether counters stop in Debug Mode.

Common Values

dcsr.stopcount
0Counters continue

Hart-local counters increment as usual in Debug Mode.

1Counters frozen

Hart-local counters do not increment while in Debug Mode or on EBREAK instructions that cause entry into Debug Mode.

↗Open Official Manual
9

stoptime

RW

Whether timers stop in Debug Mode.

stoptime (bit 9) — Whether timers stop in Debug Mode.

What This Field Controls

  • - Whether timers stop in Debug Mode.

Common Values

dcsr.stoptime
0Timers continue

Timers increment as usual in Debug Mode.

1Timers frozen

Timers do not increment in Debug Mode; an implementation may hardwire this bit to 0.

↗Open Official Manual
8:6

cause

RO

Cause code for entering Debug Mode.

cause (bits 8:6) — Cause code for entering Debug Mode.

What This Field Controls

  • - Cause code for entering Debug Mode.

Common Values

dcsr.cause
0Reserved

Reserved encoding; portable software must not depend on its meaning.

1EBREAK

Debug Mode was entered because of an EBREAK instruction.

2Trigger

Debug Mode was entered because of the trigger module.

3Halt request

Debug Mode was entered because of a debugger halt request.

4Step

Debug Mode was entered because of single-step execution.

5Reset halt request

Debug Mode was entered directly out of reset because of a reset halt request.

6Halt group

Debug Mode was entered because of a halt group request.

7Other / extended cause

Debug Mode was entered for another reason; if extcause is implemented, extcause may provide a more specific reason.

↗Open Official Manual
2

step

RW

Single-step execution control.

step (bit 2) — Single-step execution control.

What This Field Controls

  • - Single-step execution control.

Common Values

dcsr.step
0No single step

No single-step execution is requested after resume.

1Single step

After resume, the hart executes one instruction and re-enters Debug Mode.

↗Open Official Manual
1:0

prv

RW

Privilege level used when resuming execution.

prv (bits 1:0) — Privilege level used when resuming execution.

What This Field Controls

  • - Privilege level used when resuming execution.

Common Values

dcsr.prv
0User

Resume execution at User privilege level.

1Supervisor

Resume execution at Supervisor privilege level.

2Reserved

Reserved privilege-level encoding; portable software must not write or depend on it.

3Machine

Resume execution at Machine privilege level.

↗Open Official Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart and debug implementation provide dcsr.
  • - dcsr is in the 0x7B0-0x7BF Debug-mode-only CSR range; ordinary M-mode software must not treat it as a directly accessible Machine CSR.
  • - Access it only in Debug mode or in a context defined by the Debug Specification, and interpret fields according to the debug spec and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

After entering Debug mode, read dcsr according to the Debug Specification.

2

Modify only target debug fields and preserve unchanged or implementation-defined fields.

3

Validate the setting through resume, single-step, or debug-module behavior.