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CSR Bit Fields

RISC-V dscratch0 CSR Register

Address 0x7B2Privilege Debug mode onlyAccess RW / DXLEN (the widest XLEN supported by the hart)Debug, trace, and trigger CSRs

dscratch0 at 0x7B2 is Debug scratch register 0 for temporary debug-mode context.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand dscratch0 By Bit Fields

1 key fields
DXLEN-1:0

dscratch0

RW

Optional Debug scratch register. A debugger may write it only when hartinfo explicitly declares it, because the Debug Module may use it internally.

dscratch0 (bits DXLEN-1:0) — Optional Debug scratch register. A debugger may write it only when hartinfo explicitly declares it, because the Debug Module may use it internally.

What This Field Controls

  • - Optional Debug scratch register. A debugger may write it only when hartinfo explicitly declares it, because the Debug Module may use it internally.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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What To Check First When Reading This CSR

  • - First confirm that the current hart and debug implementation provide dscratch0.
  • - dscratch0 is in the 0x7B0-0x7BF Debug-mode-only CSR range; ordinary M-mode software must not treat it as a directly accessible Machine CSR.
  • - Access it only in Debug mode or in a context defined by the Debug Specification, and interpret fields according to the debug spec and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

After entering Debug mode, read dscratch0 according to the Debug Specification.

2

Modify only target debug fields and preserve unchanged or implementation-defined fields.

3

Validate the setting through resume, single-step, or debug-module behavior.