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CSR Bit Fields

RISC-V dscratch1 CSR Register

Address 0x7B3Privilege Debug mode onlyAccess RW / DXLENDebug, trace, and trigger CSRs

dscratch1 at 0x7B3 is an optional Debug-mode scratch register 1 for implementation use.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand dscratch1 By Bit Fields

1 key fields
DXLEN-1:0

VALUE

RW

Full DXLEN-wide read/write scratch value of dscratch1. This register is optional, and the Debug Module may use it internally.

VALUE (bits DXLEN-1:0) — Full DXLEN-wide read/write scratch value of dscratch1. This register is optional, and the Debug Module may use it internally.

What This Field Controls

  • - Full DXLEN-wide read/write scratch value of dscratch1. This register is optional, and the Debug Module may use it internally.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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What To Check First When Reading This CSR

  • - dscratch1 is optional; an attempt to access an unimplemented Core Debug Register raises an illegal-instruction exception.
  • - dscratch1 is in the 0x7B0-0x7BF Debug-mode-only CSR range and is accessible only from Debug Mode.
  • - A debugger may write dscratch1 only when hartinfo explicitly mentions it, because the Debug Module may use it internally.

Risk Checks Before Writing

  • - A debugger may write dscratch1 only when hartinfo explicitly mentions it; the Debug Module may use this register internally.

Put It Back Into A Real Flow

1

Confirm whether the hart's Debug Module provides dscratch1 through hartinfo.

2

Access dscratch1 only from Debug Mode.

3

Have a debugger write it only when hartinfo explicitly mentions dscratch1.