RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V hgeip CSR Register

Address 0xE12Privilege HypervisorAccess HRO / HSXLENHypervisor and virtualization CSRs

hgeip is a Hypervisor guest external interrupt-pending CSR.

Related Search Terms
hgeip CSRhgeip 0xE12guest external interrupt-pending bitsHypervisor
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
GUEST_EXTERNAL_INTERRUPT-PENDING_BITS63:1RORESERVED_ZERO0RO0
Field Map

Understand hgeip By Bit Fields

2 key fields
HSXLEN-1:1

GUEST_EXTERNAL_INTERRUPT-PENDING_BITS

RO

The guest external interrupt-pending bits of hgeip.

GUEST_EXTERNAL_INTERRUPT-PENDING_BITS (bits HSXLEN-1:1) — The guest external interrupt-pending bits of hgeip.

What This Field Controls

  • - The guest external interrupt-pending bits of hgeip.

Common Values

implemented GEILEN source bit
0Not pending

Only for implemented hgeip[GEILEN:1] bits: the corresponding virtual hart has no pending guest external interrupt; all other bits read as zero.

1Pending

Only for implemented hgeip[GEILEN:1] bits: the corresponding virtual hart has a pending guest external interrupt; each bit summarizes all pending interrupts reported by the interrupt controller for that virtual hart.

↗Open Official Manual
0

RESERVED_ZERO

RO0

Reserved bit; reads as zero whether or not GEILEN is zero.

RESERVED_ZERO (bit 0) — Reserved bit; reads as zero whether or not GEILEN is zero.

What This Field Controls

  • - Reserved bit; reads as zero whether or not GEILEN is zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hgeip is an HSXLEN-wide read-only CSR reporting pending guest external interrupts for this hart. GEILEN may be zero, and bit 0 plus all unimplemented bits read as zero.

hgeip address, access class, and width are checked against the official CSR tables: 0xE12, HRO, HSXLEN.
GEILEN is UNSPECIFIED and may be zero; when nonzero, GEILEN:1 are implemented and all other bits read as zero.
Each implemented bit summarizes pending guest external interrupts for one virtual hart; query the interrupt controller to distinguish individual interrupts.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

  • - hgeip is a Hypervisor-level CSR; its separate address is in the official HRO access class.
  • - GEILEN, the number of implemented guest-external-interrupt bits, is UNSPECIFIED and may be zero; apart from bit 0, low-order bits are implemented first.

Risk Checks Before Writing

  • - hgeip is read-only; software should not write it.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm the H extension and the GEILEN range implemented by this hart.

3

Read hgeip to observe pending state; query the interrupt controller to distinguish individual interrupts for one virtual hart.

FAQ

Can hgeip be accessed through a supervisor CSR alias?

No. hgeip is an H-level read-only CSR that reports guest external interrupts collected and reported by the interrupt controller for this hart.