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CSR Bit Fields

RISC-V mimpid CSR Register

Address 0xF13Privilege MachineAccess RO / XLENMachine implementation and hart identification CSRs

mimpid (0xF13) is an MXLEN-bit read-only Machine CSR providing a unique encoding of the processor implementation version.

Related Search Terms
mimpid CSRmimpid 0xF13machine implementation IDimplementation versionRISC-V mimpidread only machine CSR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand mimpid By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

The complete MXLEN-bit implementation ID; its format is left to the provider of the architecture source code.

VALUE (bits XLEN-1:0) — The complete MXLEN-bit implementation ID; its format is left to the provider of the architecture source code.

What This Field Controls

  • - The complete MXLEN-bit implementation ID; its format is left to the provider of the architecture source code.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mimpid (0xF13) is an MXLEN-bit read-only Machine CSR providing a unique encoding of the processor implementation version.

A value of zero can indicate the field is not implemented; the value reflects the RISC-V processor design itself, not the surrounding system.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - This CSR must be readable in any implementation; its CSR address encoding requires Machine-mode access.

Risk Checks Before Writing

  • - This is a read-only CSR; do not write it.

Put It Back Into A Real Flow

1

Read this CSR in Machine mode.

2

Interpret the result using this page's fields and the applicable implementation or platform convention.