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CSR Bit Fields

RISC-V mhartid CSR Register

Address 0xF14Privilege MachineAccess RO / XLENMachine implementation and hart identification CSRs

mhartid (0xF14) is an MXLEN-bit read-only Machine CSR containing the integer ID of the hardware thread running the code.

Related Search Terms
mhartid CSRmhartid 0xF14machine hart IDhart identifierRISC-V mhartidread only machine CSR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RO
Field Map

Understand mhartid By Bit Fields

1 key fields
XLEN-1:0

VALUE

RO

The complete MXLEN-bit hart ID.

VALUE (bits XLEN-1:0) — The complete MXLEN-bit hart ID.

What This Field Controls

  • - The complete MXLEN-bit hart ID.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhartid (0xF14) is an MXLEN-bit read-only Machine CSR containing the integer ID of the hardware thread running the code.

Hart IDs must be unique within the execution environment; they need not be contiguous, but one hart must have ID zero.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - This CSR must be readable in any implementation; its CSR address encoding requires Machine-mode access.

Risk Checks Before Writing

  • - This is a read-only CSR; do not write it.

Put It Back Into A Real Flow

1

Read this CSR in Machine mode.

2

Interpret the result using this page's fields and the applicable implementation or platform convention.