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CSR Bit Fields

RISC-V misa CSR Register

Address 0x301Privilege MachineAccess RW / XLENMachine ISA and feature-discovery CSRs

Machine ISA register reporting ISA extensions supported by the current hart.

Related Search Terms
misa CSRmisa 0x301misa MXL fieldmisa extension bitsRISC-V ISA extensionsmachine ISA register
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
MXL63:62ROReserved61:26Extensions25:0RW
Field Map

Understand misa By Bit Fields

2 key fields
XLEN-1:XLEN-2

MXL

RO

Machine XLEN encoding: 1=32-bit, 2=64-bit, 3=Reserved.

MXL (bits XLEN-1:XLEN-2) — Machine XLEN encoding: 1=32-bit, 2=64-bit, 3=Reserved.

What This Field Controls

  • - Machine XLEN encoding: 1=32-bit, 2=64-bit, 3=Reserved.

Common Values

132-bit

Effective XLEN is 32.

264-bit

Effective XLEN is 64.

3Reserved

Reserved encoding; portable software must not write or depend on it.

25:0

Extensions

RW

One bit per standard letter extension, bit0=A, bit1=B, and so on.

Extensions (bits 25:0) — One bit per standard letter extension, bit0=A, bit1=B, and so on.

What This Field Controls

  • - One bit per standard letter extension, bit0=A, bit1=B, and so on.

Common Values

0Not implemented

The corresponding letter-extension bit is 0, meaning that standard extension is not implemented or not currently available.

1Implemented

The corresponding letter-extension bit is 1, meaning that standard extension is implemented and reported as an ISA capability.

Official Basis & Search Notes

misa is the Machine ISA CSR that reports the hart MXL base integer width and standard extension bits. Use it to discover ISA capabilities, not to configure traps or execution environment controls.

misa address, lowest access privilege, and access class are checked against the official CSR table: 0x301, Machine, RW.
The official Machine chapter defines misa as the Machine ISA register reporting MXL and extension bits.
Writing misa can change available ISA extensions and is WARL-constrained; interpret it under the Machine ISA register rules.
RISC-V Privileged Architecture ManualRISC-V Unprivileged ISA Manual

What To Check First When Reading This CSR

  • - First confirm that the current hart implements misa; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x301 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads misa to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

Can misa be accessed from any privilege level?

Do not decide from the CSR name alone. The official CSR address encoding and tables define the lowest access privilege; this entry records misa as Machine. Access with insufficient privilege or to an unimplemented CSR raises an illegal-instruction exception.

What is easiest to miss when writing misa?

Do not overwrite the whole CSR as if it were an ordinary integer. Modify only target fields, preserve unchanged bits, and follow the specification for WARL, WLRL, WPRI, or reserved fields.