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CSR Bit Fields

RISC-V misa CSR Register

Address 0x301Privilege MachineAccess RW / MXLENMachine ISA and feature-discovery CSRs

Machine ISA CSR reporting the hart MXLEN and misa extension bits; the CSR is WARL and may also read as zero.

Related Search Terms
misa CSRmisa 0x301misa MXLmisa extension bitsmisa WARLmisa I E bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
MXL63:62ROReserved61:26WARL, reads zeroExtensions25:0WARL
Field Map

Understand misa By Bit Fields

4 key fields
MXLEN-1:MXLEN-2

MXL

RO

Native base integer ISA width encoding for machine mode. If misa is nonzero, MXL gives the effective M-mode XLEN (MXLEN); lower-privilege XLEN is never greater than MXLEN.

MXL (bits MXLEN-1:MXLEN-2) — Native base integer ISA width encoding for machine mode. If misa is nonzero, MXL gives the effective M-mode XLEN (MXLEN); lower-privilege XLEN is never greater than MXLEN.

What This Field Controls

  • - Native base integer ISA width encoding for machine mode. If misa is nonzero, MXL gives the effective M-mode XLEN (MXLEN); lower-privilege XLEN is never greater than MXLEN.

Common Values

132-bit

MXLEN is 32.

264-bit

MXLEN is 64.

3Reserved

Reserved encoding.

MXLEN-3:26

Reserved

WARL, reads zero

Reserved for future use; the official specification requires all reserved bits to return zero when read.

Reserved (bits MXLEN-3:26) — Reserved for future use; the official specification requires all reserved bits to return zero when read.

What This Field Controls

  • - Reserved for future use; the official specification requires all reserved bits to return zero when read.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

25:0

Extensions

WARL

Bits 25:0 use letter positions; Table 12 defines each position as an allocated extension, reserved, or tentatively reserved. This WARL field can contain writable bits where the implementation allows modification; at reset it shall contain the maximal set of supported extensions, selecting I over E when both are available.

Extensions (bits 25:0) — Bits 25:0 use letter positions; Table 12 defines each position as an allocated extension, reserved, or tentatively reserved. This WARL field can contain writable bits where the implementation allows modification; at reset it shall contain the maximal set of supported extensions, selecting I over E when both are available.

What This Field Controls

  • - Bits 25:0 use letter positions; Table 12 defines each position as an allocated extension, reserved, or tentatively reserved. This WARL field can contain writable bits where the implementation allows modification; at reset it shall contain the maximal set of supported extensions, selecting I over E when both are available.

Common Values

0Bit clear

The corresponding feature is not reported as implemented for current M-mode behavior; however, a clear bit does not necessarily prove the feature is absent.

1Bit set

The corresponding feature is implemented. X=1 reports non-standard extensions; S/U=1 report supervisor/user mode implementation respectively.

8 / 4

I / E

I is WARL; E is RO

I is used for RV32I/RV64I and E for RV32E/RV64E. Unless misa is all read-only zero, E always reads as the complement of I; if an execution environment supports both RV32E and RV32I, software can select RV32E by clearing I.

I / E (bits 8 / 4) — I is used for RV32I/RV64I and E for RV32E/RV64E. Unless misa is all read-only zero, E always reads as the complement of I; if an execution environment supports both RV32E and RV32I, software can select RV32E by clearing I.

What This Field Controls

  • - I is used for RV32I/RV64I and E for RV32E/RV64E. Unless misa is all read-only zero, E always reads as the complement of I; if an execution environment supports both RV32E and RV32I, software can select RV32E by clearing I.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

misa is an MXLEN-bit WARL CSR reporting the base integer width and standard extension bits to M-mode. It is a rudimentary feature catalog: a set extension bit indicates the feature is implemented, but a clear bit alone does not prove the feature is absent.

The official CSR table lists misa at address 0x301 with MRW access in the Machine Trap Setup group.
The Machine ISA chapter requires misa to be readable; a zero value indicates misa is not implemented and CPU capabilities require a separate non-standard mechanism.
MXL is read-only; the Extensions field is WARL, reserved bits read zero, E is read-only and reads as the complement of I unless misa is all zero, and reset selects I when I and E are both available.
Writing misa is constrained by feature dependencies, collective WARL combinations, and IALIGN write suppression; state unique to a re-enabled extension is UNSPECIFIED unless that extension specifies otherwise.
RISC-V Privileged Architecture Manual v20241017, CSR tableRISC-V Privileged Architecture Manual v20241017, Machine ISA misa section

What To Check First When Reading This CSR

  • - misa must be readable, but an implementation may return zero to indicate that misa is not implemented; CPU capabilities then require a separate non-standard mechanism.
  • - If misa is nonzero, MXL gives the effective M-mode XLEN (MXLEN); misa itself is MXLEN bits wide.
  • - An extension bit set to 1 indicates the corresponding feature is implemented; a clear extension bit does not necessarily prove the feature is absent.

Risk Checks Before Writing

  • - misa is WARL: an implementation may restrict which extension bits are writable or make fields fixed read-only; software must read back to confirm the result.
  • - If one ISA feature depends on another, attempting to enable the dependent feature while disabling its dependency disables both; implementations may also impose collective WARL constraints on misa fields.
  • - If writing misa would increase IALIGN, for example by disabling C, and the next instruction address is not aligned to the new IALIGN, the write is suppressed and misa is left unchanged.
  • - When software re-enables a previously disabled extension, state uniquely associated with that extension is UNSPECIFIED unless the extension specifies otherwise.

Put It Back Into A Real Flow

1

M-mode software reads misa; if the value is zero, do not infer capabilities from misa and use other platform discovery mechanisms.

2

If misa is nonzero, use MXL to determine MXLEN, then use the extension bits for base ISA and privilege-mode clues.

3

When modifying extension availability, write only policy allowed by the official rules, read back the WARL result, avoid triggering IALIGN write suppression, and do not assume extension-specific state survives re-enablement.

FAQ

What does reading misa as zero mean?

The official specification permits zero to indicate that misa is not implemented. In that case, software must not infer CPU capabilities from MXL or extension bits and needs a separate non-standard mechanism.

Does a clear extension bit mean the extension is absent?

Not necessarily. The specification states that a set bit implies the feature is implemented, but the inverse is not necessarily true; a clear bit alone does not prove absence.