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CSR Bit Fields

RISC-V mscontext CSR Register

Address 0x7AAPrivilege S/HS, Machine, and Debug modeAccess RW / XLENDebug trigger CSRs

Optional Sdtrig CSR that is a legacy compatibility alias of scontext.

Related Search Terms
mscontext CSRmscontext 0x7AAscontext aliasSdtrig
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SCONTEXT alias63:0WARL
Field Map

Understand mscontext By Bit Fields

1 key fields
XLEN-1:0

SCONTEXT alias

WARL

Alias of scontext; supported context values and writable bits are implementation-defined.

SCONTEXT alias (bits XLEN-1:0) — Alias of scontext; supported context values and writable bits are implementation-defined.

What This Field Controls

  • - Alias of scontext; supported context values and writable bits are implementation-defined.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mscontext is a legacy compatibility alias of scontext.

Accessible only in S/HS, Machine, and Debug mode.
New implementations are generally not expected to support this encoding.
RISC-V Debug Specification v1.0

What To Check First When Reading This CSR

  • - This is an optional Sdtrig compatibility encoding; new implementations are expected not to support it, and new debuggers should use scontext when available.
  • - It is accessible only in S/HS, Machine, and Debug mode.

Risk Checks Before Writing

  • - Accessing an unimplemented Trigger Module register raises an illegal-instruction exception.
  • - Read back after writing to determine the WARL context value accepted by the implementation.

Put It Back Into A Real Flow

1

Prefer scontext.

2

Use mscontext only for legacy debugger compatibility when the implementation provides it.