RISC-V mvienh CSR Register

Address 0x318Privilege MachineAccess MRW / RV32 high-half / 32-bitMachine AIA, timer, and indirect interrupt CSRs

AIA RV32 high-half CSR for the upper 32 bits of mvien.

Related Search Terms

mvienh CSR mvienh 0x318 RISC-V AIA virtual interrupt RV32 high half

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32MVIENH31:0MRW

Field Map

Understand mvienh By Bit Fields

1 key fields

31:0

MVIENH

MRW

mvienh fields as defined by AIA; detailed bit encoding follows the official AIA specification.

MVIENH (bits 31:0) — mvienh fields as defined by AIA; detailed bit encoding follows the official AIA specification.

What This Field Controls

- mvienh fields as defined by AIA; detailed bit encoding follows the official AIA specification.

Common Values

mvienh high-half enable bits

0Disabled

Only for official AIA-defined RV32 mvien[63:32] high-half bits implemented as valid: 0 means the corresponding virtual interrupt is disabled; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Enabled

Only for official AIA-defined RV32 mvien[63:32] high-half bits implemented as valid: 1 means the corresponding virtual interrupt is enabled; delivery also depends on pending, global interrupt, delegation, virtualization, and interrupt-controller state.

Official Basis & Search Notes

AIA RV32 high-half CSR for the upper 32 bits of mvien.

The official AIA table lists mvienh at 0x318, with MRW access and RV32 high-half / 32-bit width.

mvienh is an RV32-only high-half CSR.

This page avoids older generic trap/debug wording.

RISC-V Advanced Interrupt Architecture: Added CSRs

What To Check First When Reading This CSR

- Check mvienh address, access class, and width against the official AIA CSR table.
- Do not assign fixed meaning to reserved bits or unimplemented interrupt bits.

Risk Checks Before Writing

- Modify only target fields and preserve reserved or undefined bits.
- Confirm AIA/IMSIC and the relevant supervisor-level support before relying on this CSR.

Put It Back Into A Real Flow

Confirm that the hart implements AIA and the relevant component such as S-mode or IMSIC.

Read mvienh and interpret it according to the AIA definition for virtual interrupts.

Use only the listed official fields as portable facts; handle other bits according to the implementation and specification.

FAQ

Is mvienh a standard AIA CSR?

Yes. This page follows the address, access class, and width in the official AIA CSR table.

Can unlisted mvienh bits be written freely?

No. Reserved, unimplemented, and implementation-defined bits must be handled according to the official specification and implementation requirements.