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CSR Bit Fields

RISC-V mvienh CSR Register

Address 0x318Privilege Machine (RV32 only)Access MRW (individual bits may be read-only) / 32 bits mapped to interrupts 32-63; RV32 onlyMachine AIA, timer, and indirect interrupt CSRs

`mvienh` (0x318) is the MRW CSR that accesses the upper 32 bits of 64-bit `mvien` (interrupts 32-63) on an RV32 hart with S-mode. AIA requires the high-half CSR for such an implementation, although all accessed bits may be read-only zero.

Related Search Terms
mvienh CSRmvienh 0x318mvien upper 32 bitsmvienh interrupts 32-63mvienh RV32Smaia high-half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt 63:32 virtual-enable bits31:0Per-bit implementation-selected: writable, read-only 0, or read-only 1
Field Map

Understand mvienh By Bit Fields

1 key fields
31:0

Interrupt 63:32 virtual-enable bits

Per-bit implementation-selected: writable, read-only 0, or read-only 1

Maps bit-for-bit to mvien[63:32] and interrupts 63-32. Each mvien bit may be writable, read-only 0, or read-only 1, with possible tighter platform or extension requirements.

Interrupt 63:32 virtual-enable bits (bits 31:0) — Maps bit-for-bit to mvien[63:32] and interrupts 63-32. Each mvien bit may be writable, read-only 0, or read-only 1, with possible tighter platform or extension requirements.

What This Field Controls

  • - Maps bit-for-bit to mvien[63:32] and interrupts 63-32. Each mvien bit may be writable, read-only 0, or read-only 1, with possible tighter platform or extension requirements.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mvienh is not independent state; it is the RV32 high-half view of mvien[63:32] (interrupts 32-63).

Exists only on an RV32 hart with S-mode; width 32, access class MRW.
Bits 31:0 map exactly to mvien[63:32].
Under that applicability condition the CSR must exist, but all accessed bits may be read-only zero.
RISC-V AIA v1.0 (20250312), Control and Status Registers: Machine-level CSRsRISC-V AIA v1.0 (20250312), Machine/Supervisor Interrupts: Interrupt filtering and virtual interrupts for supervisor levelRISC-V Privileged Architecture v20260120, Currently allocated machine-level CSR addresses

What To Check First When Reading This CSR

  • - This CSR exists only on RV32; RV64 accesses the full 64-bit value through the low-address CSR.
  • - On an RV32 hart with S-mode, AIA requires this high-half CSR to exist but permits all of its bits to be read-only zero.
  • - Bit n corresponds to mvien[n+32] and interrupt n+32.

Risk Checks Before Writing

  • - Do not assume every bit in 31:0 is writable; apply mvien implementation choices for interrupts 32-63 per bit.
  • - Do not access this RV32-only CSR on RV64.

Put It Back Into A Real Flow

1

Confirm an RV32 hart with S-mode and Smaia.

2

Map target interrupt n (32-63) to mvienh bit n-32.

3

Apply the implementation-selected writable/read-only behavior for that mvien bit.

FAQ

Does mvienh exist on RV64?

No. RV64 accesses the full 64-bit value directly through mvien; mvienh is an RV32-only high-half CSR.