RISC-V mvien CSR Register

Address 0x308Privilege MachineAccess MRW / 64Machine AIA, timer, and indirect interrupt CSRs

AIA machine virtual interrupt-enable CSR for filtering and controlling supervisor-level virtual interrupts.

Related Search Terms

mvien CSR mvien 0x308 RISC-V AIA virtual interrupt interrupt control

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

MVIEN63:0MRW

Field Map

Understand mvien By Bit Fields

1 key fields

63:0

MVIEN

MRW

mvien fields as defined by AIA; detailed bit encoding follows the official AIA specification.

MVIEN (bits 63:0) — mvien fields as defined by AIA; detailed bit encoding follows the official AIA specification.

What This Field Controls

- mvien fields as defined by AIA; detailed bit encoding follows the official AIA specification.

Common Values

mvien virtual-enable bits

0Disabled

Only for official AIA-defined mvien bits implemented as valid: 0 means the corresponding virtual interrupt is disabled; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Enabled

Only for official AIA-defined mvien bits implemented as valid: 1 means the corresponding virtual interrupt is enabled; delivery also depends on pending, global interrupt, delegation, virtualization, and interrupt-controller state.

Official Basis & Search Notes

AIA machine virtual interrupt-enable CSR for filtering and controlling supervisor-level virtual interrupts.

The official AIA table lists mvien at 0x308, with MRW access and 64 width.

mvien is a 64-bit machine-level AIA CSR.

This page avoids older generic trap/debug wording.

RISC-V Advanced Interrupt Architecture: Added CSRs

What To Check First When Reading This CSR

- Check mvien address, access class, and width against the official AIA CSR table.
- Do not assign fixed meaning to reserved bits or unimplemented interrupt bits.

Risk Checks Before Writing

- Modify only target fields and preserve reserved or undefined bits.
- Confirm AIA/IMSIC and the relevant supervisor-level support before relying on this CSR.

Put It Back Into A Real Flow

Confirm that the hart implements AIA and the relevant component such as S-mode or IMSIC.

Read mvien and interpret it according to the AIA definition for virtual interrupts.

Use only the listed official fields as portable facts; handle other bits according to the implementation and specification.

FAQ

Is mvien a standard AIA CSR?

Yes. This page follows the address, access class, and width in the official AIA CSR table.

Can unlisted mvien bits be written freely?

No. Reserved, unimplemented, and implementation-defined bits must be handled according to the official specification and implementation requirements.