RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mvien CSR Register

Address 0x308Privilege MachineAccess MRW / 64-bit logical CSR; on RV32, mvien holds the low 32 bits and mvienh the high 32 bitsMachine AIA, timer, and indirect interrupt CSRs

`mvien` (0x308) is a 64-bit MRW CSR provided by Smaia when S-mode is implemented. It determines which `mvip` virtual-pending bits are active and visible at supervisor level, rather than simply masking interrupts like `mie`.

Related Search Terms
mvien CSRmvien 0x308mvien SEI SSImvien LCOFImvien midelegSmaia interrupt filtering
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt 63:14 virtual-enable bits63:14Implementation-selected: writable, read-only 0, or read-only 1Reserved0Read-only 0
Field Map

Understand mvien By Bit Fields

7 key fields
63:14

Interrupt 63:14 virtual-enable bits

Implementation-selected: writable, read-only 0, or read-only 1

Each bit corresponds to the same-numbered interrupt. An implementation may make each bit writable, read-only 0, or read-only 1; a platform standard or another extension may impose tighter requirements.

Interrupt 63:14 virtual-enable bits (bits 63:14) — Each bit corresponds to the same-numbered interrupt. An implementation may make each bit writable, read-only 0, or read-only 1; a platform standard or another extension may impose tighter requirements.

What This Field Controls

  • - Each bit corresponds to the same-numbered interrupt. An implementation may make each bit writable, read-only 0, or read-only 1; a platform standard or another extension may impose tighter requirements.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

13

LCOFI virtual enable

Implementation-dependent; must be writable with Smcdeleg+Sscofpmf+Smaia

Corresponds to local-counter-overflow interrupt LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

LCOFI virtual enable (bit 13) — Corresponds to local-counter-overflow interrupt LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

What This Field Controls

  • - Corresponds to local-counter-overflow interrupt LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

Common Values

mvien[13]
0Inactive

When writable, 0 does not activate interrupt 13 through mvien.

1Active

When writable, 1 can make mvip[13] visible at supervisor level, subject to the combined rule with mideleg[13].

12:10

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bits 12:10) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

9

SEI virtual enable

Writable or read-only 0

Corresponds to supervisor external interrupt (SEI). It cannot be read-only 1, and the specification strongly recommends making it writable. With mideleg[9]=0 and this bit=1, sip[9] aliases mvip[9] and sie[9] is writable.

SEI virtual enable (bit 9) — Corresponds to supervisor external interrupt (SEI). It cannot be read-only 1, and the specification strongly recommends making it writable. With mideleg[9]=0 and this bit=1, sip[9] aliases mvip[9] and sie[9] is writable.

What This Field Controls

  • - Corresponds to supervisor external interrupt (SEI). It cannot be read-only 1, and the specification strongly recommends making it writable. With mideleg[9]=0 and this bit=1, sip[9] aliases mvip[9] and sie[9] is writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

8:2

Reserved

Read-only 0

AIA reserves mvien bits for interrupts 2-8, including interrupt 5; they must read as zero.

Reserved (bits 8:2) — AIA reserves mvien bits for interrupts 2-8, including interrupt 5; they must read as zero.

What This Field Controls

  • - AIA reserves mvien bits for interrupts 2-8, including interrupt 5; they must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

1

SSI virtual enable

Writable or read-only 0

Corresponds to supervisor software interrupt (SSI). It cannot be read-only 1. If mip.SSIP can be set automatically by an interrupt controller, the specification strongly recommends making this bit writable.

SSI virtual enable (bit 1) — Corresponds to supervisor software interrupt (SSI). It cannot be read-only 1. If mip.SSIP can be set automatically by an interrupt controller, the specification strongly recommends making this bit writable.

What This Field Controls

  • - Corresponds to supervisor software interrupt (SSI). It cannot be read-only 1. If mip.SSIP can be set automatically by an interrupt controller, the specification strongly recommends making this bit writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

0

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bit 0) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mvien selects which mvip bits can act as supervisor-level virtual interrupt sources; together with mideleg it determines sip/sie aliasing and writability.

Only bits 1, 9, and 13-63 can be set to one; all other bits are read-only zero.
Bits 13-63 are generally implementation-selected; Smcdeleg+Sscofpmf+Smaia requires writable LCOFI bit 13.
mvien is not an mie-style interrupt mask.
RISC-V AIA v1.0 (20250312), Control and Status Registers: Machine-level CSRsRISC-V AIA v1.0 (20250312), Machine/Supervisor Interrupts: Interrupt filtering and virtual interrupts for supervisor levelRISC-V Privileged Architecture v20260120, Currently allocated machine-level CSR addressesRISC-V Privileged Architecture v20260120, Smcdeleg/Ssccfg: Virtualizing Local-Counter-Overflow Interrupts

What To Check First When Reading This CSR

  • - Each bit corresponds to interrupt number 0-63; only bits 1, 9, and 13-63 can be set to one.
  • - mvien does not exist without S-mode; with S-mode, the minimum permitted implementation may make every mvien bit read-only zero.
  • - For bits 13-63, distinguish implementation-selected writable, read-only-zero, and read-only-one behavior.

Risk Checks Before Writing

  • - With mideleg[n]=0, changing mvien[n] from 0 to 1 makes the corresponding sie[n] value UNSPECIFIED.
  • - With mvien[n]=1, changing mideleg[n] from 1 to 0 likewise makes the corresponding sie[n] value UNSPECIFIED.
  • - Write only specification-permitted bits; bits 0, 2-8, and 10-12 must remain zero.

Put It Back Into A Real Flow

1

Confirm S-mode and Smaia; on RV32, use mvienh for the upper 32 bits.

2

For the target interrupt number, inspect the matching bits in mideleg, mvien, and mvip.

3

After changing delegation or virtual enable state, re-establish the matching sie bit as required instead of relying on an UNSPECIFIED old value.

FAQ

Does mvien[n]=1 directly deliver an interrupt?

No. With mideleg[n]=0 it makes mvip[n] visible through sip[n] and makes sie[n] writable; an actual trap still depends on pending, enable, and privilege-level interrupt rules.