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CSR Bit Fields

RISC-V mvip CSR Register

Address 0x309Privilege MachineAccess MRW (individual bits include aliases and read-only behavior) / 64-bit logical CSR; on RV32, mvip holds the low 32 bits and mviph the high 32 bitsMachine AIA, timer, and indirect interrupt CSRs

`mvip` (0x309) is a 64-bit MRW virtual-interrupt-pending CSR provided by Smaia when S-mode is implemented. It provides pending state for supervisor-level interrupt filtering and virtual interrupts, together with the specified low-bit aliases for SSIP, STIP, and SEIP.

Related Search Terms
mvip CSRmvip 0x309mvip SSIP STIP SEIPmvip LCOFImvip mvien aliasSmaia virtual interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt 63:14 virtual-pending bits63:14Conditionally writable or read-only 0Reserved0Read-only 0
Field Map

Understand mvip By Bit Fields

9 key fields
63:14

Interrupt 63:14 virtual-pending bits

Conditionally writable or read-only 0

Each bit corresponds to the same-numbered interrupt. If the matching mvien bit is read-only zero, the specification recommends that this mvip bit also be read-only zero; all other bits in 13-63 must be writable.

Interrupt 63:14 virtual-pending bits (bits 63:14) — Each bit corresponds to the same-numbered interrupt. If the matching mvien bit is read-only zero, the specification recommends that this mvip bit also be read-only zero; all other bits in 13-63 must be writable.

What This Field Controls

  • - Each bit corresponds to the same-numbered interrupt. If the matching mvien bit is read-only zero, the specification recommends that this mvip bit also be read-only zero; all other bits in 13-63 must be writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

13

LCOFI virtual pending

Conditionally writable; must be writable with Smcdeleg+Sscofpmf+Smaia

Corresponds to LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

LCOFI virtual pending (bit 13) — Corresponds to LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

What This Field Controls

  • - Corresponds to LCOFI (interrupt 13). When Smcdeleg, Sscofpmf, and Smaia are all implemented, this bit must be implemented and writable.

Common Values

mvip[13]
0Not pending

When writable, 0 means virtual LCOFI is not pending.

1Pending

When writable, 1 means virtual LCOFI is pending.

12:10

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bits 12:10) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

9

SEIP virtual pending

Alias of the software-writable mip.SEIP bit or independently writable

When mvien[9]=0, this bit directly accesses the software-writable mip.SEIP bit. When mvien[9]=1, it is separated from mip.SEIP and independently writable. Changing mvien[9] does not change this bit.

SEIP virtual pending (bit 9) — When mvien[9]=0, this bit directly accesses the software-writable mip.SEIP bit. When mvien[9]=1, it is separated from mip.SEIP and independently writable. Changing mvien[9] does not change this bit.

What This Field Controls

  • - When mvien[9]=0, this bit directly accesses the software-writable mip.SEIP bit. When mvien[9]=1, it is separated from mip.SEIP and independently writable. Changing mvien[9] does not change this bit.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

8:6

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bits 8:6) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

5

STIP pending alias

Alias of mip.STIP or read-only 0

When mip.STIP is writable, this bit aliases it. When mip.STIP is not writable (for example, when menvcfg.STCE=1), this bit is read-only zero.

STIP pending alias (bit 5) — When mip.STIP is writable, this bit aliases it. When mip.STIP is not writable (for example, when menvcfg.STCE=1), this bit is read-only zero.

What This Field Controls

  • - When mip.STIP is writable, this bit aliases it. When mip.STIP is not writable (for example, when menvcfg.STCE=1), this bit is read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

4:2

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bits 4:2) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

1

SSIP virtual pending

Alias of mip.SSIP or independently writable

When mvien[1]=0, this bit aliases mip.SSIP. When mvien[1]=1, it becomes an independently writable bit. Changing mvien[1] from 0 to 1 makes this bit UNSPECIFIED.

SSIP virtual pending (bit 1) — When mvien[1]=0, this bit aliases mip.SSIP. When mvien[1]=1, it becomes an independently writable bit. Changing mvien[1] from 0 to 1 makes this bit UNSPECIFIED.

What This Field Controls

  • - When mvien[1]=0, this bit aliases mip.SSIP. When mvien[1]=1, it becomes an independently writable bit. Changing mvien[1] from 0 to 1 makes this bit UNSPECIFIED.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

0

Reserved

Read-only 0

Reserved by AIA and must read as zero.

Reserved (bit 0) — Reserved by AIA and must read as zero.

What This Field Controls

  • - Reserved by AIA and must read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mvip provides supervisor-level virtual pending state; low SSIP/STIP/SEIP bits have distinct mip alias rules, while high bits depend on how matching mvien bits are implemented.

mvip[1] and mvip[9] alias or separate according to mvien[1]/[9].
mvip[5] aliases mip.STIP only when mip.STIP is writable; otherwise it is read-only zero.
Smcdeleg+Sscofpmf+Smaia requires implemented, writable LCOFI bit 13.
RISC-V AIA v1.0 (20250312), Control and Status Registers: Machine-level CSRsRISC-V AIA v1.0 (20250312), Machine/Supervisor Interrupts: Interrupt filtering and virtual interrupts for supervisor levelRISC-V Privileged Architecture v20260120, Currently allocated machine-level CSR addressesRISC-V Privileged Architecture v20260120, Smcdeleg/Ssccfg: Virtualizing Local-Counter-Overflow Interrupts

What To Check First When Reading This CSR

  • - Each bit corresponds to interrupt number 0-63, but within 12:0 all bits except 1, 5, and 9 are reserved and read-only zero.
  • - mvip does not exist without S-mode.
  • - With S-mode, the minimum implementation need only retain mvip[1], mvip[9], and sometimes mvip[5] as aliases of existing writable mip bits; all other bits may be read-only zero.

Risk Checks Before Writing

  • - After mvien[1] changes from 0 to 1, mvip[1] is UNSPECIFIED and software must explicitly establish the desired state.
  • - Do not treat mvip[5] as an independent virtual STIP bit; it only aliases writable mip.STIP, otherwise it reads zero.
  • - Changing mvien[9] does not change mvip[9], but it changes the bit's relationship with mip.SEIP.

Put It Back Into A Real Flow

1

Confirm S-mode and Smaia; on RV32, use mviph for interrupts 32-63.

2

For the interrupt number, check mvien and mideleg to determine whether the mvip bit is visible through sip.

3

Apply the separate SSIP, STIP, and SEIP alias rules before writing a bit that is independently writable.

FAQ

Are all 64 mvip bits writable?

No. Within 12:0 only bits 1, 5, and 9 have defined semantics and they include alias/read-only cases; writability of 13-63 also depends on matching mvien bits and extension requirements.