RISC-V mviph CSR Register

Address 0x319Privilege Machine (RV32 only)Access MRW (individual bits may be read-only) / 32 bits mapped to interrupts 32-63; RV32 onlyMachine AIA, timer, and indirect interrupt CSRs

`mviph` (0x319) is the MRW CSR that accesses the upper 32 bits of 64-bit `mvip` (interrupts 32-63) on an RV32 hart with S-mode. AIA requires the high-half CSR for such an implementation, although all accessed bits may be read-only zero.

Related Search Terms

mviph CSR mviph 0x319 mvip upper 32 bits mviph interrupts 32-63 mviph RV32 Smaia high-half

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Interrupt 63:32 virtual-pending bits31:0Per-bit conditionally writable or read-only 0

Field Map

Understand mviph By Bit Fields

1 key fields

31:0

Interrupt 63:32 virtual-pending bits

Per-bit conditionally writable or read-only 0

Maps bit-for-bit to mvip[63:32] and interrupts 63-32. If the matching mvien bit is read-only zero, the specification recommends this bit also be read-only zero; all other bits in 13-63 must be writable.

Interrupt 63:32 virtual-pending bits (bits 31:0) — Maps bit-for-bit to mvip[63:32] and interrupts 63-32. If the matching mvien bit is read-only zero, the specification recommends this bit also be read-only zero; all other bits in 13-63 must be writable.

What This Field Controls

- Maps bit-for-bit to mvip[63:32] and interrupts 63-32. If the matching mvien bit is read-only zero, the specification recommends this bit also be read-only zero; all other bits in 13-63 must be writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mviph is not independent state; it is the RV32 high-half view of mvip[63:32] (interrupts 32-63).

Exists only on an RV32 hart with S-mode; width 32, access class MRW.

Bits 31:0 map exactly to mvip[63:32].

Under that applicability condition the CSR must exist, but all accessed bits may be read-only zero.

RISC-V AIA v1.0 (20250312), Control and Status Registers: Machine-level CSRs RISC-V AIA v1.0 (20250312), Machine/Supervisor Interrupts: Interrupt filtering and virtual interrupts for supervisor level RISC-V Privileged Architecture v20260120, Currently allocated machine-level CSR addresses

What To Check First When Reading This CSR

- This CSR exists only on RV32; RV64 accesses the full 64-bit value through the low-address CSR.
- On an RV32 hart with S-mode, AIA requires this high-half CSR to exist but permits all of its bits to be read-only zero.
- Bit n corresponds to mvip[n+32] and interrupt n+32.

Risk Checks Before Writing

- Do not assume every bit in 31:0 is writable; apply mvip conditional rules for interrupts 32-63 per bit.
- Do not access this RV32-only CSR on RV64.

Put It Back Into A Real Flow

Confirm an RV32 hart with S-mode and Smaia.

Map target interrupt n (32-63) to mviph bit n-32.

Use the matching mvien bit behavior to determine whether the mvip bit is writable.

FAQ

Does mviph exist on RV64?

No. RV64 accesses the full 64-bit value directly through mvip; mviph is an RV32-only high-half CSR.