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CSR Bit Fields

RISC-V scountinhibit CSR Register

Address 0x120Privilege SupervisorAccess RW / 32Supervisor counters and overflow CSRs

scountinhibit (0x120) is defined by Smcdeleg/Ssccfg as a masked alias of the 32-bit mcountinhibit for S-mode access to inhibit bits of delegated counters.

Related Search Terms
scountinhibit CSRscountinhibit 0x12032-bit inhibitSmcdelegmcountinhibit aliascounter inhibit
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32INHIBIT_ALIAS31:0RW / non-delegated bits RO 0
Field Map

Understand scountinhibit By Bit Fields

1 key fields
31:0

INHIBIT_ALIAS

RW / non-delegated bits RO 0

For counters delegated to S-mode, the matching mcountinhibit bits are accessible through scountinhibit; bits for non-delegated counters read as zero.

INHIBIT_ALIAS (bits 31:0) — For counters delegated to S-mode, the matching mcountinhibit bits are accessible through scountinhibit; bits for non-delegated counters read as zero.

What This Field Controls

  • - For counters delegated to S-mode, the matching mcountinhibit bits are accessible through scountinhibit; bits for non-delegated counters read as zero.

Common Values

delegated inhibit bit
0Counting allowed

Only for a corresponding mcountinhibit bit delegated to S-mode and accessible through scountinhibit: 0 means that counter is not inhibited by this bit; non-delegated bits read as zero and do not have this writable meaning.

1Counting inhibited

Only for a corresponding mcountinhibit bit delegated to S-mode and accessible through scountinhibit: 1 means that counter is inhibited from incrementing; non-delegated bits read as zero and do not have this writable meaning.

↗Open Official Manual
Official Basis & Search Notes

scountinhibit is not an independent counter-configuration register; it is a masked alias of the 32-bit mcountinhibit exposing only inhibit bits for counters delegated to S-mode.

Smcdeleg/Ssccfg requires menvcfg.CDE for related access.
scountinhibit is a masked alias of mcountinhibit; mcountinhibit is a 32-bit WARL counter-inhibit register.
scountinhibit bits for non-delegated counters are read-only zero.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Smcdeleg/SsccfgRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements Smcdeleg/Ssccfg; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - scountinhibit is a masked alias of the 32-bit mcountinhibit, not an XLEN-wide ordinary state CSR.
  • - Bits for non-delegated counters read as zero; delegated bits follow mcountinhibit inhibit semantics.

Risk Checks Before Writing

  • - When menvcfg.CDE=0, accessing scountinhibit raises an illegal-instruction exception.
  • - When Supervisor Counter Delegation is enabled, VS/VU-mode access to scountinhibit raises a virtual-instruction exception.

Put It Back Into A Real Flow

1

Confirm Smcdeleg/Ssccfg is available and menvcfg.CDE permits S-mode access to delegated-counter state.

2

Read scountinhibit to inspect inhibit bits for delegated counters; treat non-delegated bits as read-only zero.

3

Write inhibit bits only for delegated counters and read back to confirm the effective value.

FAQ

How does scountinhibit differ from scounteren?

scountinhibit controls inhibit bits for delegated counters; scounteren controls whether U-mode may read counters.