RISC-V stimecmp CSR Register

Address 0x14DPrivilege SupervisorAccess RW / 64Supervisor AIA, timer, and indirect interrupt CSRs

stimecmp (0x14D) is the Sstc 64-bit Supervisor timer-compare CSR; with menvcfg.STCE=1, time >= stimecmp creates the STIP pending condition; STCE=0 restores STIP behavior as if Sstc were absent.

Related Search Terms

stimecmp CSR stimecmp 0x14D Sstc timer STIP interrupt stimecmph high half Supervisor timer menvcfg STCE mcounteren TM

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

TIME_COMPARE63:0RW

Field Map

Understand stimecmp By Bit Fields

1 key fields

63:0

TIME_COMPARE

64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

TIME_COMPARE (bits 63:0) — 64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

What This Field Controls

- 64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

stimecmp is the S-mode timer compare value provided by Sstc. With menvcfg.STCE=1, STIP reflects time >= stimecmp with eventual, possibly delayed updates; STCE=0 restores STIP behavior as if Sstc were absent.

The official definition makes stimecmp 64-bit; RV32 uses stimecmp/stimecmph for the low/high 32-bit halves.

S-mode access is controlled by menvcfg.STCE and mcounteren.TM; when STCE=0, STIP reverts to its behavior as if Sstc were not implemented.

With menvcfg.STCE=1, STIP reflects the comparison between stimecmp and time and is delivered according to standard interrupt-enable and delegation rules; STCE=0 restores behavior as if Sstc were absent.

A handler that advances stimecmp must tolerate an occasional spurious timer interrupt.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Sstc RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

- stimecmp has Supervisor as its lowest access level. Instructions accessing nonexistent CSRs are reserved and do not qualify for the following virtual-instruction exception. Insufficient privilege to access an implemented CSR normally raises illegal instruction; with H, VU access to an implemented supervisor CSR raises virtual instruction when the same read/write would be allowed in HS-mode, assuming mstatus.TVM=0.
- When Sstc is implemented, S/HS-mode access to stimecmp requires menvcfg.STCE=1 and mcounteren.TM=1; if either gate is zero, access below M-mode raises an illegal-instruction exception.
- Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

- Writing a value less than or equal to current time makes STIP pending; writing a value greater than time clears the timer-interrupt condition.
- After stimecmp is updated, STIP changes are eventually reflected but not necessarily immediately; a handler may see an occasional spurious timer interrupt after return.

Put It Back Into A Real Flow

Read time or let the scheduler choose the next S-mode tick.

Confirm that Sstc is implemented and that menvcfg.STCE plus mcounteren.TM permit S-mode access to stimecmp.

Write stimecmp, and maintain stimecmph for the upper half on RV32, to set the next compare point.

Handle STIP through standard interrupt-enable and delegation rules; do not assume STIP falls immediately.

FAQ

Is stimecmp XLEN-wide?

No. The official Sstc text defines it as 64-bit; RV32 accesses it in halves through stimecmp and stimecmph.

Does writing stimecmp clear STIP immediately?

Writing a value greater than time clears the comparison condition, but the STIP change is guaranteed only eventually, not immediately.