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CSR Bit Fields

RISC-V stimecmp CSR Register

Address 0x14DPrivilege SupervisorAccess RW / 64Supervisor AIA, timer, and indirect interrupt CSRs

stimecmp (0x14D) is the 64-bit Supervisor timer-compare CSR defined by Sstc; STIP becomes pending when time is greater than or equal to stimecmp.

Related Search Terms
stimecmp CSRstimecmp 0x14DSstc timerSTIP interruptstimecmph high halfSupervisor timermenvcfg STCEmcounteren TM
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
TIME_COMPARE63:0RW
Field Map

Understand stimecmp By Bit Fields

1 key fields
63:0

TIME_COMPARE

RW

64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

TIME_COMPARE (bits 63:0) — 64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

What This Field Controls

  • - 64-bit supervisor timer-compare value; on RV32 the low 32 bits are accessed through stimecmp and the upper 32 bits through stimecmph.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

stimecmp is the S-mode timer compare value provided by Sstc. The comparison is time >= stimecmp; STIP updates are eventually visible but may not be immediate.

The official definition makes stimecmp 64-bit; RV32 uses stimecmp/stimecmph for the low/high 32-bit halves.
S-mode access is controlled by menvcfg.STCE and mcounteren.TM; when STCE=0, STIP reverts to its behavior as if Sstc were not implemented.
STIP reflects the comparison between stimecmp and time and is delivered according to standard interrupt-enable and delegation rules.
A handler that advances stimecmp must tolerate an occasional spurious timer interrupt.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - SstcRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements the extension containing stimecmp; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - S-mode may access stimecmp only when Sstc is implemented, menvcfg.STCE=1, and mcounteren.TM=1; otherwise less-than-M-mode access raises an illegal-instruction exception.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - Writing a value less than or equal to current time makes STIP pending; writing a value greater than time clears the timer-interrupt condition.
  • - After stimecmp is updated, STIP changes are eventually reflected but not necessarily immediately; a handler may see an occasional spurious timer interrupt after return.

Put It Back Into A Real Flow

1

Read time or let the scheduler choose the next S-mode tick.

2

Confirm that Sstc is implemented and that menvcfg.STCE plus mcounteren.TM permit S-mode access to stimecmp.

3

Write stimecmp, and maintain stimecmph for the upper half on RV32, to set the next compare point.

4

Handle STIP through standard interrupt-enable and delegation rules; do not assume STIP falls immediately.

FAQ

Is stimecmp XLEN-wide?

No. The official Sstc text defines it as 64-bit; RV32 accesses it in halves through stimecmp and stimecmph.

Does writing stimecmp clear STIP immediately?

Writing a value greater than time clears the comparison condition, but the STIP change is guaranteed only eventually, not immediately.